Searched full:matrix (Results 1 – 25 of 137) sorted by relevance
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742 …rnal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to…744 …_CH) /*!< ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to…745 …_CH) /*!< ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to…747 …_CH) /*!< ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to…994 …MP3 output and routed through switches COMP1_SW1 and VCOMP to ADC switch matrix. (Note: OPAMP3 is …1128 …rnal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to…1129 …rnal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to…1130 …rnal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to…1132 …toring of ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to…1133 …toring of ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to…[all …]
91 * switch matrix (ADC channel VCOMP, channel 26) and COMP1 non-inverting input99 * ADC switch matrix (ADC channel VCOMP, channel 26) and COMP1 non-inverting
475 …ANNEL_VOPAMP1 ADC_CHANNEL_3 /* Internal connection from OPAMP1 output to ADC switch matrix */476 …ANNEL_VOPAMP2 ADC_CHANNEL_8 /* Internal connection from OPAMP2 output to ADC switch matrix */478 …ANNEL_VOPAMP3 ADC_CHANNEL_13 /* Internal connection from OPAMP3 output to ADC switch matrix */
702 * they share the ADC switch matrix.741 * and OPAMP3 output to ADC switch matrix (ADC channel VCOMP, channel
525 uint32_t BasicCyclesNbr; /*!< Specifies the number of basic cycles in the system matrix.534 …uint32_t ExpTxTrigNbr; /*!< Specifies the number of expected Tx_Triggers in the system matrix.826 …AN_TTIR_TXU /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */827 …AN_TTIR_TXO /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle */1426 #define FDCAN_TT_CYCLES_PER_MATRIX_1 ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix */1427 #define FDCAN_TT_CYCLES_PER_MATRIX_2 ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix */1428 #define FDCAN_TT_CYCLES_PER_MATRIX_4 ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix */1429 #define FDCAN_TT_CYCLES_PER_MATRIX_8 ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix */1430 #define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */1431 #define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */[all …]
516 uint32_t BasicCyclesNbr; /*!< Specifies the nubmer of basic cycles in the system matrix.525 …uint32_t ExpTxTrigNbr; /*!< Specifies the number of expected Tx_Triggers in the system matrix.757 …AN_TTIR_TXU /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */758 …AN_TTIR_TXO /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle */1354 #define FDCAN_TT_CYCLES_PER_MATRIX_1 ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix */1355 #define FDCAN_TT_CYCLES_PER_MATRIX_2 ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix */1356 #define FDCAN_TT_CYCLES_PER_MATRIX_4 ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix */1357 #define FDCAN_TT_CYCLES_PER_MATRIX_8 ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix */1358 #define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */1359 #define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */[all …]
292 int16_t RR; /*!< Coefficient Row 1 Column 1 of the matrix294 int16_t RG; /*!< Coefficient Row 1 Column 2 of the matrix296 int16_t RB; /*!< Coefficient Row 1 Column 3 of the matrix300 int16_t GR; /*!< Coefficient Row 2 Column 1 of the matrix302 int16_t GG; /*!< Coefficient Row 2 Column 2 of the matrix304 int16_t GB; /*!< Coefficient Row 2 Column 3 of the matrix308 int16_t BR; /*!< Coefficient Row 3 Column 1 of the matrix310 int16_t BG; /*!< Coefficient Row 3 Column 2 of the matrix312 int16_t BB; /*!< Coefficient Row 3 Column 3 of the matrix
10 matrix:17 python-version: ${{ matrix.python-version }}36 name: coverage-${{ matrix.python-version }}
34 ADC since they share the ADC switch matrix: COMP1 non-inverting35 input is routed through ADC switch matrix. Except if ADC is intended389 /* through ADC switch matrix. */ in HAL_COMP_Init()410 /* Close the analog switch of ADC switch matrix to COMP1 (ADC */ in HAL_COMP_Init()478 /* Open the analog switch of ADC switch matrix to COMP1 (ADC */ in HAL_COMP_DeInit()
166 (+) Stop mode: bus matrix clocks stalled, the oscillators can be stopped.171 (+) LP-Stop mode: bus matrix clocks stalled, the oscillators can be stopped.178 (+) LPLV-Stop mode: bus matrix clocks stalled, the oscillators can be stopped.
585 In DSTOP mode the domain bus matrix clock is stopped.615 In DStop mode the domain bus matrix clock is stopped.648 (+) The domain bus matrix clock is stopped.719 * @note In STOP mode, the domain bus matrix clock is stalled.792 * @note In DStop mode the domain bus matrix clock is stopped.
244 /** @defgroup AXIM_AMIB_READ_ISSUING_BM_CAP AXIM AMIBs Read Issuing Bus Matrix Capability253 /** @defgroup AXIM_AMIB_WRITE_ISSUING_BM_CAP AXIM AMIBs Write Issuing Bus Matrix Capability
5184 /* Set Coefficient row 1 columns 1 2 3 and the added column of the matrix */ in HAL_DCMIPP_PIPE_SetISPColorConversionConfig()5198 /* Set Coefficient row 2 columns 1 2 3 and the added column of the matrix */ in HAL_DCMIPP_PIPE_SetISPColorConversionConfig()5211 /* Set Coefficient row 3 columns 1 2 3 and the added column of the matrix */ in HAL_DCMIPP_PIPE_SetISPColorConversionConfig()5340 /* Set Coefficient row 1 columns 1 2 3 and the added column of the matrix */ in HAL_DCMIPP_PIPE_SetYUVConversionConfig()5353 /* Set Coefficient row 2 columns 1 2 3 and the added column of the matrix */ in HAL_DCMIPP_PIPE_SetYUVConversionConfig()5366 /* Set Coefficient row 3 columns 1 2 3 and the added column of the matrix */ in HAL_DCMIPP_PIPE_SetYUVConversionConfig()7467 /* Get Coefficient row 1 columns 1 2 3 and the added column of the matrix */ in HAL_DCMIPP_PIPE_GetISPColorConversionConfig()7480 /* Get Coefficient row 2 columns 1 2 3 and the added column of the matrix */ in HAL_DCMIPP_PIPE_GetISPColorConversionConfig()7493 /* Get Coefficient row 3 columns 1 2 3 and the added column of the matrix */ in HAL_DCMIPP_PIPE_GetISPColorConversionConfig()
1196 * @brief HAL AXI Interconnect Matrix (AXIM) configuration functions1414 * @brief Configure AMIB read/write issuing bus matrix capability.
1791 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix …1794 …SH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */1797 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix …1800 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix sel…1826 …EYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */1831 …EYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */1836 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix …1841 …SH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
1799 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix …1802 …SH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */1805 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix …1808 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix sel…1834 …EYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */1839 …EYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */1844 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix …1849 …SH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
1864 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix …1867 …SH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */1870 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix …1873 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix sel…1899 …EYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */1904 …EYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */1909 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix …1914 …SH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
1992 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix …1995 …SH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */1998 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix …2001 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix sel…2027 …EYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */2032 …EYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */2037 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix …2042 …SH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
1930 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix …1933 …SH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */1936 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix …1939 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix sel…1965 …EYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */1970 …EYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */1975 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix …1980 …SH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
1783 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix …1786 …SH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */1789 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix …1792 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix sel…1818 …EYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */1823 …EYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */1828 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix …1833 …SH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
1789 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix …1792 …SH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */1795 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix …1798 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix sel…1824 …EYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */1829 …EYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */1834 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix …1839 …SH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
262 /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ in SystemInit()
261 /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ in SystemInit()
263 /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ in SystemInit()
