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/Zephyr-Core-3.5.0/tests/drivers/can/api/src/
Dcommon.h112 * @brief Standard (11-bit) CAN ID masked filter 1. This filter matches
118 * @brief Standard (11-bit) CAN ID masked filter 2. This filter matches
136 * @brief Extended (29-bit) CAN ID masked filter 1. This filter matches
142 * @brief Extended (29-bit) CAN ID masked filter 2. This filter matches
Dcommon.c132 * @brief Standard (11-bit) CAN ID masked filter 1. This filter matches
142 * @brief Standard (11-bit) CAN ID masked filter 2. This filter matches
172 * @brief Extended (29-bit) CAN ID masked filter 1. This filter matches
182 * @brief Extended (29-bit) CAN ID masked filter 2. This filter matches
/Zephyr-Core-3.5.0/drivers/interrupt_controller/
DKconfig.loapic24 interrupt that was to be dispensed has become masked (programmed
53 You don't need this if the RTEs are either all guaranteed to be masked
/Zephyr-Core-3.5.0/include/zephyr/drivers/gpio/
Dgpio_cmsdk_ahb.h49 /* Offset: 0x400 - 0x7fc lower byte masked access register (r/w) */
51 /* Offset: 0x800 - 0xbfc upper byte masked access register (r/w) */
/Zephyr-Core-3.5.0/drivers/counter/
Ddualtimer_cmsdk_apb.h26 /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
42 /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
/Zephyr-Core-3.5.0/soc/riscv/espressif_esp32/esp32c3/
Didle.c20 /* curiously it arrives here with the interrupts masked in arch_cpu_idle()
/Zephyr-Core-3.5.0/arch/xtensa/include/
Dxtensa-asm2.h18 * anything masked, so don't assume that!).
/Zephyr-Core-3.5.0/subsys/net/lib/websocket/
Dwebsocket_internal.h111 /** Is the message masked */
112 uint8_t masked : 1; member
/Zephyr-Core-3.5.0/dts/bindings/counter/
Despressif,esp32-timer.yaml51 Values above that range will be 16-bit-masked. Values 0 and 1 will be
/Zephyr-Core-3.5.0/subsys/zbus/
Dzbus.c328 const struct zbus_channel *chan, bool masked) in zbus_obs_set_chan_notification_mask() argument
344 observation_mask->enabled = masked; in zbus_obs_set_chan_notification_mask()
352 const struct zbus_channel *chan, bool *masked) in zbus_obs_is_chan_notification_masked() argument
368 *masked = observation_mask->enabled; in zbus_obs_is_chan_notification_masked()
/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_pcal64xxa.c65 uint16_t masked; member
209 int_sources |= ((input_port ^ drv_data->input_port_last) & ~drv_data->triggers.masked); in pcal64xxa_process_input()
362 triggers.masked |= BIT(pin); in pcal64xxa_pin_interrupt_configure()
364 triggers.masked &= ~BIT(pin); in pcal64xxa_pin_interrupt_configure()
507 uint8_t input_latch = ~triggers->masked; in pcal6408a_triggers_apply()
508 uint8_t interrupt_mask = triggers->masked; in pcal6408a_triggers_apply()
676 uint16_t input_latch = ~triggers->masked; in pcal6416a_triggers_apply()
677 uint16_t interrupt_mask = triggers->masked; in pcal6416a_triggers_apply()
751 .masked = 0xFFFF, in pcal64xxa_init()
Dgpio_xlnx_ps_bank.c137 * @brief Masked write of a bit mask for the entire GPIO pin bank.
139 * Performs a masked write operation on the data register of
145 * bank's data register. The masked data word read from the
146 * RO data register and the masked data word provided by the
/Zephyr-Core-3.5.0/drivers/ipm/
Dipm_stm32_hsem.c63 /* Clear semaphore rx_semid interrupt status and masked status */ in stm32_hsem_mailbox_ipm_rx_isr()
140 /* Clear semaphore rx_semid interrupt status and masked status */ in stm32_hsem_mailbox_ipm_set_enabled()
/Zephyr-Core-3.5.0/arch/xtensa/core/
Dirq_manage.c23 * Valid values are from 1 to 6. Interrupts of priority 1 are not masked when
/Zephyr-Core-3.5.0/tests/subsys/zbus/unittests/src/
Dmain.c649 bool masked = false; in ZTEST() local
667 zassert_equal(-EFAULT, zbus_obs_is_chan_notification_masked(NULL, NULL, &masked), NULL); in ZTEST()
669 zassert_equal(-EFAULT, zbus_obs_is_chan_notification_masked(&fast_lis, NULL, &masked), in ZTEST()
672 zassert_equal(-EFAULT, zbus_obs_is_chan_notification_masked(NULL, &aux1_chan, &masked), in ZTEST()
676 zbus_obs_is_chan_notification_masked(&not_observing_sub, &aux1_chan, &masked), in ZTEST()
686 zassert_equal(count_fast, 0, "Count must 0, since the channel notification is masked"); in ZTEST()
697 zassert_equal(count_fast, 3, "Must be 3. The channel notification was masked %d", in ZTEST()
/Zephyr-Core-3.5.0/boards/posix/native_posix/
Dirq_ctrl.c28 * If an interrupt is masked in this way, it will be pending in the premask in
230 * We always awake the CPU even if the IRQ was masked, in irq_raising_from_hw_now()
/Zephyr-Core-3.5.0/drivers/ethernet/
Deth_dwmac_mmu.c80 /* set up IRQs (still masked for now) */ in dwmac_platform_init()
/Zephyr-Core-3.5.0/dts/bindings/serial/
Dst,stm32-uart-base.yaml58 configured masked at boot (sm32wl55 for instance), preventing the device to wakeup
/Zephyr-Core-3.5.0/drivers/timer/
Dapic_tsc.c21 uint8_t masked : 1; member
186 lvt_reg.lvt.masked = 0; in sys_clock_driver_init()
/Zephyr-Core-3.5.0/scripts/native_simulator/native/src/
Dirq_ctrl.c27 * If an interrupt is masked in this way, it will be pending in the premask in
238 * We always awake the CPU even if the IRQ was masked, in irq_raising_from_hw_now()
/Zephyr-Core-3.5.0/kernel/include/
Dkswap.h90 * masked and switch away to begin scheduling) and the case of in do_swap()
95 * can sometimes run with interrupts masked in ways that don't in do_swap()
/Zephyr-Core-3.5.0/include/zephyr/xen/public/
Devent_channel.h44 * notifications are masked until the bit is cleared again (therefore,
48 * Event notifications can be masked by setting a flag; this is
/Zephyr-Core-3.5.0/arch/x86/core/ia32/
Dcrt0.S159 * Note that all floating point exceptions are masked by default,
174 * Note that all SSE exceptions are masked by default,
297 .long 0x1f80 /* all SSE exceptions clear & masked */
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/
Dadsp_interrupt.h66 uint16_t is[32]; /* status (potentially masked by ie) */
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/
Dadsp_interrupt.h64 uint16_t is[32]; /* status (potentially masked by ie) */

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