Home
last modified time | relevance | path

Searched full:load (Results 1 – 25 of 550) sorted by relevance

12345678910>>...22

/Zephyr-Core-3.5.0/samples/subsys/shell/devmem_load/
DREADME.md1 # Zephyr devmem load command
2 This module add a `devmem load` command that allows data to be loaded into device memory.
3 The `devmem load` command is supported by every transport the shell can run on.
9 Note: when using the devmem load command over UART it is recommended to use interrupts whenever pos…
30 The `devmem load` command can now be used (`devmem load [option] [address]`):
32 uart:~$ devmem load 0x20020000
37 Now, the `devmem load` is waiting for data.
51 Currently, the `devmem load` command supports the following argument:
/Zephyr-Core-3.5.0/samples/subsys/settings/
DREADME.rst5 Load and save configuration values using the settings API.
59 basic load and save using registered handlers
61 load all key-value pairs using registered handlers
67 load <alpha/beta> key-value pairs using registered handlers
75 load all key-value pairs using registered handlers
82 direct load: <alpha/length/2>
83 direct load: <alpha/length/1>
84 direct load: <alpha/length>
92 immediate load: OK.
95 Can't to load the <alpha/length> value as expected
/Zephyr-Core-3.5.0/boards/riscv/longan_nano/
Dboard.cmake6 board_runner_args(openocd "--cmd-pre-load=gd32vf103-pre-load")
7 board_runner_args(openocd "--cmd-load=gd32vf103-load")
/Zephyr-Core-3.5.0/samples/drivers/fpga/fpga_controller/
DREADME.rst4 Load a bitstream into an FPGA and perform basic operations on it.
8 This module is an FPGA driver that can easily load a bitstream, reset it, check its status, enable …
47 See :ref:`quickfeather` on how to load an image to the board.
68 The FPGA controller command can now be used (``fpga load <device> <address> <size in bytes>``):
72 uart:~$ fpga load FPGA 0x2001a46c 75960
85 To load a bitstream into device memory, use `devmem load` command.
90 uart:~$ devmem load -e 0x10000
114 uart:~$ fpga load FPGA 0x10000 75960
/Zephyr-Core-3.5.0/arch/xtensa/core/
Dfatal.c47 return "load/store error"; in z_xtensa_exccause()
57 return "load/store alignment"; in z_xtensa_exccause()
61 return "load/store PIF data error"; in z_xtensa_exccause()
65 return "load/store PIF addr error"; in z_xtensa_exccause()
75 return "load/store TLB miss"; in z_xtensa_exccause()
77 return "load/store TLB multi hit"; in z_xtensa_exccause()
79 return "load/store privilege"; in z_xtensa_exccause()
81 return "load prohibited"; in z_xtensa_exccause()
Ddebug_helpers_asm.S26 /* Load address for interrupted stack */
28 /* Load i PC in a7 */
32 /* Load value for (i-1) PC, which return address of i into a7 */
/Zephyr-Core-3.5.0/tests/arch/arc/arc_dsp_sharing/src/
Dload_store.c9 * @brief load/store portion of DSP sharing test
13 * This module implements the load/store portion of the DSP sharing test. This
16 * The load/store test validates the dsp unit context
31 /* space for dsp register load/store area used by low priority task */
35 /* space for dsp register load/store area used by high priority thread */
41 /* Indicates that the load/store test exited */
48 * @brief Low priority DSP load/store thread
63 * Initialize dsp load buffer to known values; in load_store_low()
81 * Utilize an architecture specific function to load all the in load_store_low()
87 * Waste some cycles to give the high priority load/store in load_store_low()
[all …]
/Zephyr-Core-3.5.0/samples/boards/arc_secure_services/
DREADME.rst85 The bootloader should load the secure and normal application into the correct place,
91 Use the gdb debugger to load and run the two applications.
97 # load secure application first
100 # load normal application
123 # load normal application
124 $ load ../../../philosophers/build/zephyr/zephyr.elf
125 # load secure application
126 $ load
/Zephyr-Core-3.5.0/soc/arm/nordic_nrf/nrf53/
DKconfig.soc120 prompt "LFXO load capacitance"
125 bool "Use external load capacitors"
128 bool "6 pF internal load capacitance"
131 bool "7 pF internal load capacitance"
134 bool "9 pF internal load capacitance"
139 prompt "HFXO load capacitance"
152 bool "Use external load capacitors"
155 bool "Use internal load capacitors"
161 int "Doubled value of HFXO internal load capacitors (in pF)"
/Zephyr-Core-3.5.0/tests/arch/arc/arc_dsp_sharing/
DREADME.txt7 1) Test load and store dsp registers (including arch specific registers)
25 Load and store OK after 0 (high) + 84 (low) tests
26 Load and store OK after 100 (high) + 11926 (low) tests
27 Load and store OK after 200 (high) + 23767 (low) tests
28 Load and store OK after 300 (high) + 35607 (low) tests
29 Load and store OK after 400 (high) + 47448 (low) tests
30 Load and store OK after 500 (high) + 59287 (low) tests
/Zephyr-Core-3.5.0/scripts/pylib/twister/
Dscl.py33 Safely load a YAML document
38 :param str filename: filename to load
45 return yaml.load(f, Loader=SafeLoader)
74 Safely load a testcase/sample yaml document and validate it
77 :param str filename: name of the file to load and process
78 :param dict schema: loaded YAML schema (can load with :func:`yaml_load`)
/Zephyr-Core-3.5.0/tests/kernel/fpu_sharing/generic/src/
Dload_store.c10 * @brief load/store portion of FPU sharing test
16 * This module implements the load/store portion of the FPU sharing test. This
19 * The load/store test validates the floating point unit context
34 * to load ALL non-integer registers, but main() should validate that only the
82 /* space for float register load/store area used by low priority task */
86 /* space for float register load/store area used by high priority thread */
96 /* Indicates that the load/store test exited */
103 * @brief Low priority FPU load/store thread
121 * Initialize floating point load buffer to known values; in load_store_low()
139 * Utilize an architecture specific function to load all the in load_store_low()
[all …]
/Zephyr-Core-3.5.0/drivers/counter/
Dtimer_dtmr_cmsdk_apb.c39 uint32_t load; member
48 cfg->dtimer->timer1load = data->load; in dtmr_cmsdk_apb_start()
71 *ticks = data->load - cfg->dtimer->timer1value; in dtmr_cmsdk_apb_get_value()
85 data->load = top_cfg->ticks; in dtmr_cmsdk_apb_set_top_value()
90 * Write to background load register will not affect in dtmr_cmsdk_apb_set_top_value()
96 * Write to load register will also set in dtmr_cmsdk_apb_set_top_value()
113 uint32_t ticks = data->load; in dtmr_cmsdk_apb_get_top_value()
198 .load = UINT_MAX, \
Ddualtimer_cmsdk_apb.h16 /* Offset: 0x000 (R/W) Timer 1 Load */
28 /* Offset: 0x018 (R/W) Background Load Register */
32 /* Offset: 0x020 (R/W) Timer 2 Load */
44 /* Offset: 0x038 (R/W) Background Load Register */
/Zephyr-Core-3.5.0/drivers/watchdog/
Dwdt_rpi_pico.c26 uint32_t load; member
64 watchdog_hw->load = data->load; in wdt_rpi_pico_setup()
117 data->load = (cfg->window.max * USEC_PER_MSEC * RPI_PICO_WDT_TIME_MULTIPLICATION_FACTOR); in wdt_rpi_pico_install_timeout()
137 watchdog_hw->load = data->load; in wdt_rpi_pico_feed()
164 .load = (CONFIG_WDT_RPI_PICO_INITIAL_TIMEOUT * \
/Zephyr-Core-3.5.0/dts/bindings/fpga/
Dlattice,ice40-fpga.yaml11 load-mode:
15 Configure the method used to load the bitstream.
17 0 := load the FPGA via SPI transfer
18 1 := load the FPGA via bit-banged GPIO
24 load-mode = <0>;
/Zephyr-Core-3.5.0/dts/bindings/test/
Dvnd,busy-sim.yaml5 CPU load simulator
19 Debug pin is set to active state when cpu load is active.
/Zephyr-Core-3.5.0/boards/arm/lpcxpresso54114/
Dboard.cmake8 board_runner_args(jlink "--device=LPC54114J256_M4" "--reset-after-load")
10 board_runner_args(jlink "--device=LPC54114J256_M0" "--reset-after-load")
/Zephyr-Core-3.5.0/tests/kernel/fpu_sharing/generic/
DREADME.txt7 1) load and store floating point registers and check for corruption
60 Load and store OK after 0 (high) + 63 (low) tests
61 Load and store OK after 100 (high) + 6540 (low) tests
62 Load and store OK after 200 (high) + 12965 (low) tests
63 Load and store OK after 300 (high) + 19366 (low) tests
64 Load and store OK after 400 (high) + 25756 (low) tests
65 Load and store OK after 500 (high) + 32128 (low) tests
/Zephyr-Core-3.5.0/arch/x86/zefi/
DREADME.txt21 Arguably this is needlessly inefficient, having to load the whole
23 load it from the EFI boot filesystem into its correct location with no
51 in ELF get found via GOT and PLT tables that are populated at load
67 they ignore the preferred load address and will put the image at
80 that the EFI environment will load our image at an address that
83 physical memory, while Zephyr prefers to load into the bottom of RAM
/Zephyr-Core-3.5.0/dts/bindings/rtc/
Dnxp,kinetis-pit.yaml27 max-load-value:
30 description: maximum load value supported
/Zephyr-Core-3.5.0/drivers/timer/
Dcortex_m_systick.c24 * reliably" -- it becomes the minimum value of the LOAD register, and
83 * re-program the SysTick.LOAD register, in sys_clock_set_timeout().
90 * - reprogramming of SysTick.LOAD must be clearing the SysTick.COUNTER
163 /* In TICKLESS mode, the SysTick.LOAD is re-programmed in sys_clock_isr()
167 * If a timer wrap occurs right when we re-program LOAD, in sys_clock_isr()
170 * because the value has been updated before LOAD re-program. in sys_clock_isr()
244 SysTick->LOAD = last_load - 1; in sys_clock_set_timeout()
248 * Add elapsed cycles while computing the new load to cycle_count. in sys_clock_set_timeout()
252 * close to LOAD, then there are little chances to catch val2 between in sys_clock_set_timeout()
253 * val1 and LOAD after a wrap. COUNTFLAG should be checked in addition. in sys_clock_set_timeout()
[all …]
/Zephyr-Core-3.5.0/boards/riscv/longan_nano/support/
Dopenocd.cfg19 proc gd32vf103-pre-load {} {
23 proc gd32vf103-load {file} {
/Zephyr-Core-3.5.0/boards/riscv/hifive1/
Dboard.cmake18 board_runner_args(openocd --cmd-load "hifive1-load")
/Zephyr-Core-3.5.0/samples/boards/qomu/
DREADME.rst6 This sample demonstrates how to load bitstream on EOS-S3 FPGA and use the
27 To load example into Qomu you can use `TinyFPGA-Programmer-Application <https://github.com/QuickLog…
33 …f8841bdc1ed35c1539ac381182159d7cd5914/doc/Qomu_UserGuide.pdf>`_ on how to load an image to the boa…

12345678910>>...22