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/hal_intel-latest/docs/
Dbsp_sedi_doxyfile6 # All text after a double hash (##) is considered a comment and is placed in
7 # front of the TAG it is preceding.
9 # All text after a single hash (#) is considered a comment and will be ignored.
10 # The format is:
21 # file that follow. The default is UTF-8 which is also the encoding used for all
25 # The default value is: UTF-8.
29 # The PROJECT_NAME tag is a single word (or a sequence of words surrounded by
31 # project for which the documentation is generated. This name is used in the
33 # The default value is: My Project.
39 # control system is used.
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/hal_intel-latest/bsp_sedi/include/driver/
Dsedi_driver_uart.h302 * to guarantee that the UART interface is available.
306 * The returned status is to be interpreted using the sedi_uart_status_t for
318 * This is a blocking synchronous call.
333 * This is a blocking synchronous call.
349 * Perform a read on the UART interface. This is a blocking
354 * @param[OUT] data buffer where data is to be read.This must not be NULL.
370 * This is a non-blocking synchronous call.
384 * This is a non-blocking synchronous call.
397 * Perform a write on the UART interface. This is a blocking
417 * is already in progress.API user should terminate any ongoing async writes
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Dsedi_driver_i2c.h357 * \param[in] pending: i2c data transfer operation is pending
371 * \param[in] pending: i2c data transfer operation is pending
387 * \param[in] pending: i2c data transfer operation is pending
406 * \param[in] pending: i2c data transfer operation is pending
426 * \param[in] pending: i2c data transfer operation is pending
440 * \param[in] pending: i2c data transfer operation is pending
452 * -1 when slave is not addressed by master
Dsedi_driver_ipc.h39 * An ipc busy bit is cleared by peer
46 * An ipc message is received by peer
190 * param[in] msg: point to memory area where data is stored
Dsedi_driver_spi.h65 * The parameter range is [1,16]
92 * The parameter is bitmask of CS pin been controlled by SPI
152 * event is SEDI_SPI_EVENT_TX_FINISHED or SEDI_SPI_EVENT_RX_FINISHED.
264 uint32_t isr : 6; /* ISR status in error, only bit 0-5 is valid */
Dsedi_driver_hpet.h169 * \param[in] one_shot: if it is a one_shot timer
Dsedi_driver_common.h102 * \brief Driver is busy
Dsedi_driver_dma.h216 * \brief DMA is busy
/hal_intel-latest/zephyr/iut_test/test_zephyr/gpio/
Dtest_gpio.c23 iut_print("GPLR register is 0x%x\n", read32(regs + 0x4)); in dump_gpio_regs()
24 iut_print("GPDR register is 0x%x\n", read32(regs + 0x1C)); in dump_gpio_regs()
25 iut_print("GRER register is 0x%x\n", read32(regs + 0x64)); in dump_gpio_regs()
26 iut_print("GFER register is 0x%x\n", read32(regs + 0x7c)); in dump_gpio_regs()
27 iut_print("GIMR register is 0x%x\n", read32(regs + 0xac)); in dump_gpio_regs()
28 iut_print("GISR register is 0x%x\n", read32(regs + 0xc4)); in dump_gpio_regs()
86 iut_print("trigger callback %d times, pin index is 0x%x\n", times, pins); in test_callback()
/hal_intel-latest/
DLICENSE15 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
/hal_intel-latest/bsp_sedi/drivers/ipc/
Dsedi_ipc.c135 /* IPC is always available */ in sedi_ipc_get_capabilities()
208 * IPC is an always-on IP, no power operation available for IPC,
401 /* the peer is PMC or CSE */ in sedi_ipc_send_ack_drbl()
406 /* the peer is host */ in sedi_ipc_send_ack_drbl()
513 /* check whether it is an inbound interrupt*/ in sedi_ipc_isr()
529 /* check whether it is an outbound interrupt*/ in sedi_ipc_isr()
546 /* check whether it is a csr interrupt */ in sedi_ipc_isr()
/hal_intel-latest/bsp_sedi/soc/intel_ish/pm/
Dish_dma.c9 static int dma_init_called; /* If ish_dma_init is called */
17 * The timeout is approximately 2.2 seconds according to in dma_poll()
19 * instruction count which is around 4. in dma_poll()
Dish_pm.c90 * the alternative way is:
93 * edge expected to be triggered next time, that is, opposite to its value.
112 /* pin is high, just keep falling edge mode */ in convert_both_edge_gpio_to_single_edge()
115 /* pin is low, just keep rising edge mode */ in convert_both_edge_gpio_to_single_edge()
/hal_intel-latest/bsp_sedi/soc/intel_ish/include/
Dsedi_soc.h13 /* ISH SoC clock is lower on FPGA than Silicon */
136 * \brief check if a device is owned by SoC itself
/hal_intel-latest/bsp_sedi/drivers/usart/
Dsedi_dw_uart.c89 * This structure is only intended to be used by the sedi_uart_save_context and
113 bool context_valid; /**< Indicates whether saved context is valid. */
266 /* Wait till reset bit is cleared */ in uart_soft_rst_instance()
438 * register still is transmitting the last 8 in sedi_uart_isr_handler()
441 * is still in sedi_uart_isr_handler()
443 * is in sedi_uart_isr_handler()
458 * If we are starting the transfer then the TX FIFO is in sedi_uart_isr_handler()
474 * TX buffer is empty. in sedi_uart_isr_handler()
500 * NOTE: Returned len is 0 for now, this might in sedi_uart_isr_handler()
574 /* Remove the address from FIFO as address match is in sedi_uart_isr_handler()
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/hal_intel-latest/bsp_sedi/drivers/hpet/
Dsedi_hpet.c122 /* need to wait until INT clearing is finished, or HPET in sedi_hpet_set_comparator()
222 * Initial state of HPET is unknown, so put it back in a reset-like in sedi_hpet_init()
294 /* Check if timer is being used */ in sedi_hpet_config_timer()
/hal_intel-latest/bsp_sedi/drivers/spi/
Dsedi_spi_dw_apb.c40 * SPI Control Register is valid only when SSI_SPI_MODE is either set to
233 /* DFS: Data Frame size only valid when SSI_MAX_XFER_SIZE is configured to in lld_spi_default_config()
234 * 16, if SSI_MAX_XFER_SIZE is configured to 32, then writing to this field in lld_spi_default_config()
236 * DFS_32: only valid when SSI_MAX_XFER_SIZE is configured to 32 in lld_spi_default_config()
293 /* DFS: Data Frame size only valid when SSI_MAX_XFER_SIZE is configured to in lld_spi_config_width()
294 * 16, if SSI_MAX_XFER_SIZE is configured to 32, then writing to this field in lld_spi_config_width()
296 * DFS_32: only valid when SSI_MAX_XFER_SIZE is configured to 32 in lld_spi_config_width()
473 /* SPI_FRF: SPI Frame Format Bits RO and only valid when SSI_SPI_MODE is in lld_spi_set_line_mode()
1295 /* inst is must, address is option */ in spi_enhanced_config()
/hal_intel-latest/.github/workflows/
Diut_zephyr_build.yml24 # Actions runner is implemented. Remove this workaround when
Dcheckpatch.yml33 echo "checkpatch base is: $(git show FETCH_HEAD --oneline --raw)"
/hal_intel-latest/bsp_sedi/soc/intel_ish/
Dsedi_soc.c27 /* weak PM functions used by SEDI drivers when SEDI PM driver is not enabled */
/hal_intel-latest/bsp_sedi/drivers/gpio/
Dsedi_gpio.c399 /* The register is w1c */ in sedi_gpio_clear_gisr()
408 /* The register is w1c */ in sedi_gpio_clear_gwsr()
/hal_intel-latest/bsp_sedi/drivers/i2c/
Dsedi_i2c_dw_apb_200a.c105 * For example, standard mode is 100KHz, 10000ns per period, 5000ns for
471 /* If it is first data, need RESTART */ in i2c_ask_data()
527 /* If it is the last data for whole transfer */ in i2c_send()
1212 /* check if there is a entity in rx fifo */ in sedi_i2c_isr_handler()
1240 /*If it is read operation, need to send cmd*/ in sedi_i2c_isr_handler()
/hal_intel-latest/bsp_sedi/drivers/dma/
Dsedi_dma_ann_1p0.c408 /* source is memory*/ in dma_apply_other_regs()
420 /* destination is memory*/ in dma_apply_other_regs()
722 /* Polling mode is only used in single-block mode */
/hal_intel-latest/bsp_sedi/soc/intel_ish/pm/aon/
Daon_task.c58 * Since on x86, the IDT entry index (count from 0) is also the interrupt
696 * poll LDO_READY status to make sure SRAM LDO is on in handle_d0i2()
/hal_intel-latest/bsp_sedi/soc/common/include/
Dsedi_reg_defs.h121 * - REGR (REGister Reset value) : reset value after reset. It's const if the register is RO.