| /Zephyr-Core-3.5.0/samples/subsys/usb_c/sink/ |
| D | README.rst | 1 .. zephyr:code-sample:: usb-c-sink
2 :name: Basic USB-C Sink
3 :relevant-api: _usbc_device_api
5 Implement a USB-C Power Delivery application in the form of a USB-C Sink.
10 This example demonstrates how to create a USB-C Power Delivery application and
11 how to generate USB VIF policies in XML format using the USB-C subsystem. The
12 application implements a USB-C Sink device.
14 After the USB-C Sink device is plugged into a Power Delivery charger, it
18 .. _usb-c-sink-sample-requirements:
22 The TCPC device used by the sample is specified in the devicetree
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| /Zephyr-Core-3.5.0/dts/bindings/usb-c/ |
| D | usb-c-connector.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 A USB Type-C connector node represents a physical USB Type-C connector.
6 It should be a child of a USB-C interface controller or a separate node
7 when it is attached to both MUX and USB-C interface controller.
9 This is based on Linux, documentation:
10 …/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/connector/usb-connector.yaml?h=v5.1…
14 USB-C connector attached to a STM32 UCPD typec port controller, which has
18 compatible = "zephyr,usb-c-vbus-adc";
19 io-channels = <&adc2 8>;
20 output-ohms = <49900>;
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| /Zephyr-Core-3.5.0/soc/arm/infineon_cat1/psoc6/ |
| D | Kconfig.soc | 3 # SPDX-License-Identifier: Apache-2.0
104 Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSoC™ 6
105 dual-core MCU. The image is responsible for booting the Cortex-M4 on the device.
110 DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSoC™ 6 BLE
111 dual-core MCU.The image is provided as C array ready to be compiled as part of the Cortex-M4
112 application. The Cortex-M0+ application code is placed to internal flash by the Cortex-M4
|
| /Zephyr-Core-3.5.0/dts/bindings/mtd/ |
| D | nordic,qspi-nor.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 compatible: "nordic,qspi-nor"
9 include: [base.yaml, "jedec,spi-nor-common.yaml"]
11 on-bus: qspi
17 jedec-id:
23 The size in bits. Set this or size-in-bytes, but not both.
25 size-in-bytes:
31 quad-enable-requirements:
37 - "fastread" # Single data line SPI, FAST_READ (0x0B)
38 - "read2o" # Dual data line SPI, READ2O (0x3B)
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| /Zephyr-Core-3.5.0/soc/arm/nuvoton_npcx/ |
| D | Kconfig | 1 # Nuvoton Cortex-M4 Embedded Controller
4 # SPDX-License-Identifier: Apache-2.0
35 This is generated from the npcx BIN image.
85 Reading modes supported are normal, fast, dual, and quad.
94 bool "SPI flash operates with dual reading mode"
104 default "dual" if NPCX_HEADER_SPI_READ_MODE_DUAL
121 The core clock frequency is twice the flash clock frequency.
152 The SPI flash size is 0.5M or 1M Bytes.
157 The SPI flash size is 2M Bytes.
162 The SPI flash size is 4M Bytes.
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| /Zephyr-Core-3.5.0/soc/arm/microchip_mec/ |
| D | Kconfig | 5 # SPDX-License-Identifier: Apache-2.0
23 Boot-ROM. Use the full Microchip SPI image generator program for
24 authentication and all other Boot-ROM loader features. Refer to the MCHP
67 Reading modes supported are normal, fast, dual, and quad.
70 bool "SPI flash operates full-duplex with frequency (< 25 MHz)"
73 bool "SPI flash operates full-duplex with fast reading mode"
76 bool "SPI flash operates with dual data reading mode"
87 default "dual" if MCHP_MEC_HEADER_SPI_READ_MODE_DUAL
99 The SPI flash size is 256K Bytes.
104 The SPI flash size is 512K Bytes.
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| /Zephyr-Core-3.5.0/drivers/flash/ |
| D | flash_stm32l4x.c | 6 * SPDX-License-Identifier: Apache-2.0
37 if (regs->ACR & FLASH_ACR_DCEN) { in flush_cache()
38 regs->ACR &= ~FLASH_ACR_DCEN; in flush_cache()
40 * This bit can be written only when the data cache is disabled in flush_cache()
42 regs->ACR |= FLASH_ACR_DCRST; in flush_cache()
43 regs->ACR &= ~FLASH_ACR_DCRST; in flush_cache()
44 regs->ACR |= FLASH_ACR_DCEN; in flush_cache()
47 if (regs->ACR & FLASH_ACR_ICEN) { in flush_cache()
48 regs->ACR &= ~FLASH_ACR_ICEN; in flush_cache()
51 * is disabled in flush_cache()
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| D | flash_stm32f7x.c | 5 * SPDX-License-Identifier: Apache-2.0
29 if (regs->ACR & FLASH_ACR_ARTEN) { in flush_cache()
30 regs->ACR &= ~FLASH_ACR_ARTEN; in flush_cache()
33 * is disabled (ARTEN = 0). in flush_cache()
35 regs->ACR |= FLASH_ACR_ARTRST; in flush_cache()
36 regs->ACR &= ~FLASH_ACR_ARTRST; in flush_cache()
37 regs->ACR |= FLASH_ACR_ARTEN; in flush_cache()
46 /* if the control register is locked, do not fail silently */ in write_byte()
47 if (regs->CR & FLASH_CR_LOCK) { in write_byte()
48 return -EIO; in write_byte()
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| /Zephyr-Core-3.5.0/dts/bindings/flash_controller/ |
| D | st,stm32-ospi-nor.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 mx25lm51245: ospi-nor-flash@0 {
10 compatible = "st,stm32-ospi-nor";
12 data-mode = <OSPI_OPI_MODE>; /* access on 8 data lines */
13 data-rate = <OSPI_DTR_TRANSFER>; /* access in DTR */
14 ospi-max-frequency = <DT_FREQ_M(50)>;
19 compatible: "st,stm32-ospi-nor"
21 include: ["flash-controller.yaml", "jedec,jesd216.yaml"]
23 on-bus: ospi
28 ospi-max-frequency:
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| /Zephyr-Core-3.5.0/boards/arm/lpcxpresso54114/ |
| D | Kconfig.defconfig | 4 # SPDX-License-Identifier: Apache-2.0
12 # Place size restrictions on first image if dual core is enabled
16 DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
|
| /Zephyr-Core-3.5.0/boards/arm/mps2_an521/ |
| D | CMakeLists.txt | 4 # SPDX-License-Identifier: Apache-2.0
13 # However, if building with OPENAMP, there is no need to build
14 # any binary for CPU0, as this is built by the dual core sample.
16 set(CPU0_BINARY_DIR ${BOARD_DIR}/empty_cpu0-prefix/src/empty-cpu0-build/zephyr)
24 CMAKE_CACHE_ARGS -DBOARD:STRING=mps2_an521
|
| /Zephyr-Core-3.5.0/samples/drivers/ipm/ipm_mhu_dual_core/ |
| D | README.rst | 1 .. zephyr:code-sample:: ipm-mhu-dual-core
3 :relevant-api: ipm_interface
5 Implement inter-processor mailbox (IPM) using an MHU (Message Handling Unit)
10 the processor cores. This sample is a simple dual-core example for a
23 -----------
28 .. zephyr-app-commands::
29 :zephyr-app: samples/drivers/ipm/ipm_mhu_dual_core
37 .. zephyr-app-commands::
38 :zephyr-app: samples/drivers/ipm/ipm_mhu_dual_core
46 A third-party tool (srecord) is used to generate the Intel formatted hex image.
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| /Zephyr-Core-3.5.0/boards/arm/mec172xevb_assy6906/support/ |
| D | spi_cfg.txt | 10 ; BoardID is used by a Boot-ROM feature named PlatformID. By default PlatformID
11 ; is disabled. If PlatformID is enabled in OTP Boot-ROM will check the image
12 ; BoardID value with an OTP PlatformID value. Load is aborted if the ID's do
19 SpiReadCommand = Dual
|
| /Zephyr-Core-3.5.0/boards/arm/mec172xmodular_assy6930/support/ |
| D | spi_cfg.txt | 10 ; BoardID is used by a Boot-ROM feature named PlatformID. By default PlatformID
11 ; is disabled. If PlatformID is enabled in OTP Boot-ROM will check the image
12 ; BoardID value with an OTP PlatformID value. Load is aborted if the ID's do
19 SpiReadCommand = Dual
|
| /Zephyr-Core-3.5.0/boards/arm/pico_pi_m4/doc/ |
| D | index.rst | 3 Pico-Pi i.MX7D - Android Things IoT Development Platform
9 The i.MX7D SoC is a Hybrid multi-core processor composed of Single Cortex A7
17 :alt: Pico-Pi i.MX7D
22 The Pico-Pi Platform is composed of a CPU and IO board.
24 Pico-Pi IO Board
26 - S1 - On/Off (MX7_ONOFF signal)
27 - Board to board connector : Edison compatible connector (70 configurable pins)
28 - mikroBUS expansion connector ADC, GPIO, I²C, PWM, SPI, UART)
29 - 10-pin needle JTAG Connector
30 - Debug USB exposing One UART
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| /Zephyr-Core-3.5.0/drivers/usb/bc12/ |
| D | Kconfig.pi3usb9201 | 2 # SPDX-License-Identifier: Apache-2.0
9 This is a Dual-Role USB Charging-Type Detector. It can operate in
21 This is an emulator for the Pericom PI3USB9201 USB charging detector.
32 When this option is enabled and the charging mode is configured for
37 This is a workaround for a glitch seen on the USB data lines when
|
| /Zephyr-Core-3.5.0/doc/hardware/peripherals/ |
| D | espi.rst | 9 The eSPI (enhanced serial peripheral interface) is a serial bus that is
10 based on SPI. It also features a four-wire interface (receive, transmit, clock
11 and slave select) and three configurations: single IO, dual IO and quad IO.
14 lower pin count, and the frequency is twice as fast (66MHz vs. 33MHz)
15 Because of its enhancements, the eSPI is used to replace the LPC
27 …https://www.intel.com/content/dam/support/us/en/documents/software/chipset-software/327432-004_esp…
|
| /Zephyr-Core-3.5.0/tests/boards/mec172xevb_assy6906/qspi/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
30 * bits[15:8] = bytes number of clocks with data lines tri-stated
77 zassert_true(device_is_ready(spi_dev), "SPI controller device is not ready"); in spi_single_init()
87 * SPI clocks based on single, dual, or quad mode.
88 * mode = 1(full-duplex), 2(dual), 4(quad)
89 * full-duplex: 8 clocks per byte
90 * dual: 4 clocks per byte
113 return -EINVAL; in spi_flash_address_format()
117 dest[i] = (uint8_t)((spi_addr >> ((addrsz - (i + 1U)) * 8U)) & 0xffU); in spi_flash_address_format()
210 * - Find spi device
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| /Zephyr-Core-3.5.0/doc/connectivity/bluetooth/ |
| D | bluetooth-dev.rst | 1 .. _bluetooth-dev:
7 approach that is described in the :ref:`application` section of the
10 Additional information that is only relevant to Bluetooth applications can be
16 Calling into the Bluetooth API is intended to be thread safe, unless otherwise
18 is the case for all API calls is an ongoing one, but the overall goal is
22 .. _bluetooth-hw-setup:
28 applications with Zephyr. Depending on the hardware that is available to you,
43 that the application is targeting.
44 All the :ref:`bluetooth-configs` and :ref:`bluetooth-build-types` are supported
45 but you might need to build Zephyr more than once if you are using a dual-chip
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| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | xlnx,xps-gpio-1.00.a.yaml | 3 compatible: "xlnx,xps-gpio-1.00.a"
5 include: [gpio-controller.yaml, base.yaml]
7 bus: xlnx,xps-gpio-1.00.a
10 # https://github.com/Xilinx/device-tree-xlnx
16 xlnx,all-inputs:
21 xlnx,all-outputs:
26 xlnx,dout-default:
29 Default output value. If n-th bit is 1, GPIO-n default value is 1.
31 xlnx,gpio-width:
36 xlnx,tri-default:
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| /Zephyr-Core-3.5.0/boards/arm/96b_meerkat96/doc/ |
| D | index.rst | 9 96Boards Meerkat96 board is based on NXP i.MX7 Hybrid multi-core processor,
10 composed of a dual Cortex®-A7 and a single Cortex®-M4 core.
11 Zephyr OS is ported to run on the Cortex®-M4 core.
13 - Board features:
15 - RAM: 512 Mbyte
16 - Storage:
18 - microSD Socket
19 - Wireless:
21 - WiFi: 2.4GHz IEEE 802.11b/g/n
22 - Bluetooth: v4.1 (BR/EDR)
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| /Zephyr-Core-3.5.0/boards/arm/colibri_imx7d_m4/doc/ |
| D | index.rst | 3 NXP i.MX 7 Computer on Module - Colibri iMX7
9 The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual Cortex A7
17 :alt: Colibri-iMX7
22 - i.MX7 Single/Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core
24 - Memory
26 - RAM -> A7: 256MB, 512MB and 1GB
27 - RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR)
28 - Flash -> A7: 4Gb eMMC and 512Mb NAND
30 - Display
32 - RGB 1920x1080x24bpp
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| /Zephyr-Core-3.5.0/boards/arm/thingy53_nrf5340/doc/ |
| D | index.rst | 13 The nRF5340 is a dual-core SoC based on the Arm® Cortex®-M33 architecture, with:
15 * a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and
16 Armv8-M Security Extension, running at up to 128 MHz, referred to as
18 * a secondary Arm Cortex-M33 core, with a reduced feature set, running at
26 Trusted Firmware-M (TF-M) and building the ``ns`` target is not supported for this board.
37 Flashing Zephyr onto Thingy:53 requires an external J-Link programmer. The
38 programmer is attached to the P9 programming header.
43 Thingy:53 does not have an on-board J-Link debug IC as some other nRF5
52 .. target-notes::
|
| /Zephyr-Core-3.5.0/drivers/spi/ |
| D | spi_xec_qmspi_ldma.c | 4 * SPDX-License-Identifier: Apache-2.0
19 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
20 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
33 * received data is shifted off the input line(s) improperly. Received
34 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
35 * to sample input line(s) on same edge as output data is ready.
84 uint8_t width; /* 0(half) 1(single), 2(dual), 4(quad) */
122 return -ETIMEDOUT; in xec_qmspi_spin_yield()
132 * Some QMSPI timing register may be modified by the Boot-ROM OTP
143 taps[0] = regs->TM_TAPS; in qmspi_reset()
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| /Zephyr-Core-3.5.0/boards/arm/mimxrt1170_evk/ |
| D | mimxrt1170_evkb_cm7.dts | 4 * SPDX-License-Identifier: Apache-2.0
12 /delete-property/ zephyr,flash-controller;
13 /delete-property/ zephyr,code-partition;
17 /delete-property/ magn0;
18 /delete-property/ accel0;
24 /delete-node/ is25wp128@0;
29 compatible = "nxp,imx-flexspi-nor";
32 spi-max-frequency = <133000000>;
34 jedec-id = [ef 60 20];
35 erase-block-size = <4096>;
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