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/Zephyr-Core-3.5.0/dts/arm/nuvoton/npcx/npcx9/
Dnpcx9-miwus-int-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* Common MIWU group-interrupt mapping configurations in npcx family */
8 #include <nuvoton/npcx/npcx-miwus-int-map.dtsi>
10 /* Specific MIWU group-interrupt mapping configurations in npcx9 series */
13 npcx-miwus-int-map {
14 map_miwu0_groups: map-miwu0-groups {
15 compatible = "nuvoton,npcx-miwu-int-map";
18 group_a0: group-a0-map {
20 irq-prio = <2>;
21 group-mask = <0x01>;
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/Zephyr-Core-3.5.0/dts/arm/nuvoton/npcx/npcx4/
Dnpcx4-miwus-int-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* Common MIWU group-interrupt mapping configurations in npcx family */
8 #include <nuvoton/npcx/npcx-miwus-int-map.dtsi>
10 /* Specific MIWU group-interrupt mapping configurations in npcx4 series */
13 npcx-miwus-int-map {
14 map_miwu0_groups: map-miwu0-groups {
15 compatible = "nuvoton,npcx-miwu-int-map";
18 group_a0: group-a0-map {
20 irq-prio = <2>;
21 group-mask = <0x01>;
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/Zephyr-Core-3.5.0/dts/arm/nuvoton/npcx/npcx7/
Dnpcx7-miwus-int-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* Common MIWU group-interrupt mapping configurations in npcx family */
8 #include <nuvoton/npcx/npcx-miwus-int-map.dtsi>
10 /* Specific MIWU group-interrupt mapping configurations in npcx7 series */
13 npcx-miwus-int-map {
14 map_miwu0_groups: map-miwu0-groups {
15 compatible = "nuvoton,npcx-miwu-int-map";
18 group_ad0: group-ad0-map {
20 irq-prio = <2>;
21 group-mask = <0x09>;
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/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_cc13xx_cc26xx.c4 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/gpio/ti-cc13xx-cc26xx-gpio.h>
17 #include <driverlib/interrupt.h>
29 /* bits 16-18 in iocfg registers correspond to interrupt settings */
32 /* the rest are for general (non-interrupt) config */
48 uint32_t mask);
50 uint32_t mask);
72 return -ENOTSUP; in gpio_cc13xx_cc26xx_config()
92 return -ENOTSUP; in gpio_cc13xx_cc26xx_config()
106 return -EINVAL; in gpio_cc13xx_cc26xx_config()
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Dgpio_emul.c4 * SPDX-License-Identifier: Apache-2.0
27 * @brief GPIO Emulator interrupt capabilities
30 * model GPIO interrupt controllers with varying interrupt trigger support.
91 /** Interrupt status for each pin */
95 /** Is interrupt enabled for each pin */
97 /** Singly-linked list of callbacks associated with the controller */
102 * @brief Obtain a mask of pins that match all of the provided @p flags
109 * @param mask A mask of flags to match
112 * @return a mask of the pins with matching @p flags
115 get_pins_with_flags(const struct device *port, gpio_port_pins_t mask, in get_pins_with_flags() argument
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Dgpio_nxp_s32.c2 * Copyright 2022-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/gpio/nxp-s32-gpio.h>
38 struct gpio_nxp_s32_irq_map *map; member
72 const struct gpio_nxp_s32_config *port_config = dev->config; in nxp_s32_gpio_configure()
73 Siul2_Dio_Ip_GpioType *gpio_base = port_config->gpio_base; in nxp_s32_gpio_configure()
74 Siul2_Port_Ip_PortType *port_base = port_config->port_base; in nxp_s32_gpio_configure()
78 return -ENOTSUP; in nxp_s32_gpio_configure()
82 struct gpio_nxp_s32_data *data = dev->data; in nxp_s32_gpio_configure()
84 WRITE_BIT(data->pin_wkpu_mask, pin, (flags & NXP_S32_GPIO_INT_WKPU)); in nxp_s32_gpio_configure()
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Dgpio_andes_atcgpio100.c4 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/dt-bindings/gpio/andestech-atcgpio100.h>
36 #define REG_INTE 0x50 /* Interrupt enable reg. */
37 #define REG_IMD0 0x54 /* Interrupt mode 0 ~ 7 reg. */
38 #define REG_IMD1 0x58 /* Interrupt mode 8 ~ 15 reg. */
39 #define REG_IMD2 0x5C /* Interrupt mode 16 ~ 23 reg. */
40 #define REG_IMD3 0x60 /* Interrupt mode 24 ~ 31 reg. */
41 #define REG_ISTA 0x64 /* Interrupt status reg. */
42 #define REG_DEBE 0x70 /* De-bounce enable reg. */
43 #define REG_DEBC 0x74 /* De-Bounce control reg. */
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Dgpio_mchp_xec_v2.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
49 /* Each GPIO pin 32-bit control register located consecutively in memory */
52 const struct gpio_xec_config *config = dev->config; in pin_ctrl_addr()
54 return config->pcr1_base + ((uintptr_t)pin * 4u); in pin_ctrl_addr()
57 /* GPIO Parallel input is a single 32-bit register per bank of 32 pins */
60 const struct gpio_xec_config *config = dev->config; in pin_parin_addr()
62 return config->parin_addr; in pin_parin_addr()
65 /* GPIO Parallel output is a single 32-bit register per bank of 32 pins */
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Dgpio_sifive.c2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
25 /* sifive GPIO register-set structure */
50 /* multi-level encoded interrupt corresponding to pin 0 */
64 ((const struct gpio_sifive_config * const)(dev)->config)
66 ((volatile struct gpio_sifive_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
68 ((struct gpio_sifive_data *)(dev)->data)
87 * with the interrupt
97 return (plic_irq - base_irq); in gpio_sifive_plic_to_pin()
106 /* Calculate pin and mask from base level 2 line */ in gpio_sifive_irq_handler()
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/Zephyr-Core-3.5.0/dts/riscv/
Dneorv32.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/gpio/gpio.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "neorv32-cpu";
27 intc: interrupt-controller {
28 compatible = "riscv,cpu-intc";
29 interrupt-controller;
30 #address-cells = <1>;
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/Zephyr-Core-3.5.0/dts/bindings/pcie/host/
Dpci-host-ecam-generic.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "pci-host-ecam-generic"
8 include: pcie-controller.yaml
14 msi-parent:
21 As described in IEEE Std 1275-1994, but must provide at least a
22 definition of non-prefetchable memory. One or both of prefetchable Memory
25 interrupt-map-mask:
28 interrupt-map:
31 bus-range:
/Zephyr-Core-3.5.0/dts/bindings/interrupt-controller/
Dnuvoton,npcx-miwu-int-map.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NPCX-MIWU group-interrupt mapping child node
6 compatible: "nuvoton,npcx-miwu-int-map"
14 child-binding:
15 description: Child node to present the mapping between MIWU group and interrupt
21 irq-prio:
25 group-mask:
28 description: group bit-mask for miwu interrupts
31 description: groups shared the same interrupt
/Zephyr-Core-3.5.0/samples/drivers/ethernet/eth_ivshmem/boards/
Dqemu_cortex_a53.overlay4 * SPDX-License-Identifier: Apache-2.0
9 /delete-node/ memory@40000000;
12 compatible = "mmio-sram";
16 /delete-node/ pcie@4010000000;
19 compatible = "pci-host-ecam-generic";
22 #size-cells = <0x02>;
23 #address-cells = <0x03>;
25 #interrupt-cells = <0x01>;
26 interrupt-map-mask = <0x00 0x00 0x00 0x07>;
27 interrupt-map = <
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/Zephyr-Core-3.5.0/include/zephyr/drivers/pcie/
Dmsi.h4 * SPDX-License-Identifier: Apache-2.0
68 * @param priority the MSI vectors base interrupt priority
84 * @param routine Interrupt service routine
86 * @param flags Arch-specific IRQ configuration flag
106 * @return A (32-bit) value for the MSI MAP register.
119 * @return A (16-bit) value for MSI MDR register.
139 * @brief Check if the given PCI endpoint supports MSI/MSI-X
142 * @return true if the endpoint support MSI/MSI-X
154 #define PCIE_MSI_MCR_MMC 0x000E0000U /* Multi Messages Capable mask */
156 #define PCIE_MSI_MCR_MME 0x00700000U /* mask of # of enabled IRQs */
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/Zephyr-Core-3.5.0/drivers/serial/
Duart_pl011_registers.h6 * SPDX-License-Identifier: Apache-2.0
15 * UART PL011 register map structure
45 #define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
48 #define PL011_FR_CTS BIT(0) /* clear to send - inverted */
49 #define PL011_FR_DSR BIT(1) /* data set ready - inverted */
50 #define PL011_FR_DCD BIT(2) /* data carrier detect - inverted */
56 #define PL011_FR_RI BIT(8) /* ring indicator - inverted */
84 #define PL011_LCRH_WLEN_SIZE(x) (x - 5)
108 /* PL011 Control Register - vendor-specific fields */
118 /* PL011 Interrupt Fifo Level Select Register */
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/Zephyr-Core-3.5.0/drivers/sensor/bmi08x/
Dbmi08x.h5 * SPDX-License-Identifier: Apache-2.0
53 /* Accel Interrupt status0 register */
56 /* Accel Interrupt status1 register */
80 /* Accel Interrupt pin 1 configuration register */
83 /* Accel Interrupt pin 2 configuration register */
86 /* Accel Interrupt latch configuration register */
89 /* Accel Interrupt pin1 mapping register */
92 /* Accel Interrupt pin2 mapping register */
95 /* Accel Interrupt map register */
124 /* Interrupt masks */
[all …]
/Zephyr-Core-3.5.0/scripts/dts/python-devicetree/tests/
Dtest.dts4 * SPDX-License-Identifier: BSD-3-Clause
9 /dts-v1/;
16 interrupt-parent-test {
18 compatible = "interrupt-three-cell";
19 #interrupt-cells = <3>;
20 interrupt-controller;
24 interrupt-names = "foo", "bar";
25 interrupt-parent = <&{/interrupt-parent-test/controller}>;
28 interrupts-extended-test {
29 controller-0 {
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/Zephyr-Core-3.5.0/dts/x86/intel/
Dapollo_lake.dtsi2 * Copyright (c) 2017-2019 Intel Corporation.
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,apollo-lake";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
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/Zephyr-Core-3.5.0/dts/arm64/qemu/
Dqemu-virt-arm64.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 * qemu-system-aarch64 -machine virt,gic-version=host,accel=kvm
11 * -cpu cortex-a53 -nographic -machine dumpdtb=virt.dtb
13 * dtc -I dtb -O dts virt.dtb
17 #include <arm64/armv8-a.dtsi>
18 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
19 #include <zephyr/dt-bindings/pcie/pcie.h>
22 #address-cells = <2>;
23 #size-cells = <2>;
26 #address-cells = <1>;
[all …]
Dqemu-virt-a53.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 * qemu-system-aarch64 -machine virt -cpu cortex-a53 -nographic
11 * -machine dumpdtb=virt.dtb
13 * dtc -I dtb -O dts virt.dtb
17 #include <arm64/armv8-a.dtsi>
18 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
19 #include <zephyr/dt-bindings/pcie/pcie.h>
22 #address-cells = <2>;
23 #size-cells = <2>;
26 #address-cells = <1>;
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/Zephyr-Core-3.5.0/drivers/interrupt_controller/
Dintc_miwu.c4 * SPDX-License-Identifier: Apache-2.0
13 * The device Multi-Input Wake-Up Unit (MIWU) supports the Nuvoton embedded
16 * 'Level' and 'Edge' trigger type and grouping of external interrupt sources
19 * wake-up input (WUI) sources.
24 * 1. npcxn-miwus-wui-map.dtsi: it presents relationship between wake-up inputs
26 * 2. npcxn-miwus-int-map.dtsi: it presents relationship between MIWU group
27 * and NVIC interrupt in npcx series. Please notice it isn't 1-to-1 mapping.
99 static void intc_miwu_dispatch_isr(sys_slist_t *cb_list, uint8_t mask) in intc_miwu_dispatch_isr() argument
105 if (cb->io_cb.params.cb_type == NPCX_MIWU_CALLBACK_GPIO) { in intc_miwu_dispatch_isr()
106 if (BIT(cb->io_cb.params.wui.bit) & mask) { in intc_miwu_dispatch_isr()
[all …]
Dintc_sam0_eic.c4 * SPDX-License-Identifier: Apache-2.0
34 while (EIC->SYNCBUSY.reg) { in wait_synchronization()
37 while (EIC->STATUS.bit.SYNCBUSY) { in wait_synchronization()
45 EIC->CTRLA.bit.ENABLE = on; in set_eic_enable()
47 EIC->CTRL.bit.ENABLE = on; in set_eic_enable()
53 struct sam0_eic_data *const dev_data = dev->data; in sam0_eic_isr()
54 uint16_t bits = EIC->INTFLAG.reg; in sam0_eic_isr()
58 EIC->INTFLAG.reg = bits; in sam0_eic_isr()
74 * Map the EIC lines to the port pin masks based on which port is in sam0_eic_isr()
88 &dev_data->lines[line_index]; in sam0_eic_isr()
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Dintc_gicv3.c4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
33 * deal with (one configuration byte per interrupt). PENDBASE has to
49 return gic_rdists[arch_curr_cpu()->id]; in gic_get_rdist()
79 uint8_t *cfg = &((uint8_t *)lpi_prop_table)[intid - 8192]; in arm_gic_lpi_setup()
94 uint8_t *cfg = &((uint8_t *)lpi_prop_table)[intid - 8192]; in arm_gic_lpi_set_priority()
106 uint8_t *cfg = &((uint8_t *)lpi_prop_table)[intid - 8192]; in arm_gic_lpi_is_enabled()
135 uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1)); in arm_gic_irq_set_priority() local
141 /* Disable the interrupt */ in arm_gic_irq_set_priority()
142 sys_write32(mask, ICENABLER(base, idx)); in arm_gic_irq_set_priority()
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/Zephyr-Core-3.5.0/drivers/sdhc/
Dintel_emmc_host.h4 * SPDX-License-Identifier: Apache-2.0
10 /* Bit map for command Register */
18 /* Bit map for Transfer Mode Register */
31 /* Bit map for Block Size and GAP Register */
47 /* Bit Map and length details for Clock Control Register */
54 /* Bit Map for Host Control 1 Register */
179 #define GET_BITS(reg_name, start, width) ((reg_name) & (((1 << (width)) - 1) << (start)))
209 volatile uint16_t normal_int_stat; /**< Normal Interrupt Status */
210 volatile uint16_t err_int_stat; /**< Error Interrupt Status */
211 volatile uint16_t normal_int_stat_en; /**< Normal Interrupt Status Enable */
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/Zephyr-Core-3.5.0/include/zephyr/xen/public/
Dxen.h1 /* SPDX-License-Identifier: MIT */
33 #include "arch-arm.h"
178 * DOMID_IO is used to restrict page-table updates to mapping I/O memory.
179 * Although no Foreign Domain need be specified to map I/O pages, DOMID_IO
182 * aren't adjusted on the I/O-mapping code path).
191 * DOMID_XEN is used to allow privileged domains to map restricted parts of
194 * - HYPERVISOR_mmu_update()'s, HYPERVISOR_mmuext_op()'s, or
196 * - with XENMAPSPACE_gmfn_foreign,
212 /* Mask for valid domain id values */
221 * Event channel endpoints per domain (when using the 2-level ABI):
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