| /hal_xtensa-3.6.0/include/xtensa/ |
| D | traxreg.h | 64 /* TRAX ID register fields: */
70 #define TRAX_ID_MAJVER(id) (((id) >> 20) & 0x0f) argument
71 #define TRAX_ID_MINVER(id) (((id) >> 17) & 0x07) argument
72 #define TRAX_ID_VER(id) ((TRAX_ID_MAJVER(id)<<4)|TRAX_ID_MINVER(id)) argument
74 #define TRAX_ID_CFGID 0x0000ffff /* TRAX configuration ID */
77 /* Other TRAX ID register macros: */
92 #define TRAX_ID_1_0_ERRATUM(id) (TRAX_ID_VER(id) == TRAX_VER_1_0) argument
94 #define TRAX_ID_MEMSZ_ERRATUM(id) (TRAX_ID_VER(id) == TRAX_VER_2_0) argument
174 unsigned id; member
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| D | xdm-regs.h | 51 #define XDM_TRAX_ID 0x100000 /*[0x00] ID */
110 #define XDM_OCD_ID 0x102000 /*[0x40] ID register */
134 #define XDM_MISC_UBID 0x103038 /*[0x5E] [INTERNAL] Build Unique ID */
135 #define XDM_MISC_CID 0x10303C /*[0x5F] [INTERNAL] Customer ID */
144 #define XDM_CS_DEV_ID 0x103FC8 /*[0x72] Device ID */
146 #define XDM_CS_PER_ID4 0x103FD0 /*[0x74] Peripheral ID reg byte 4 */
147 #define XDM_CS_PER_ID5 0x103FD4 /*[0x75] Peripheral ID reg byte 5 */
148 #define XDM_CS_PER_ID6 0x103FD8 /*[0x76] Peripheral ID reg byte 6 */
149 #define XDM_CS_PER_ID7 0x103FDC /*[0x77] Peripheral ID reg byte 7 */
150 #define XDM_CS_PER_ID0 0x103FE0 /*[0x78] Peripheral ID reg byte 0 */
[all …]
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| D | overlay_os_asm.h | 2 // $Id$
78 // (SP - 24) Overlay ID to restore
123 // If we get here then a restore is needed. Save the overlay ID, PC and PS.
129 s32e \ovreg, \spreg, -24 // Save overlay ID
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| D | trax-api.h | 45 int trax_version; /* TRAX_ID_VER(id), one of TRAX_VER_xxx macros */
78 extern int trax_display_id(unsigned id, const char *prefix);
79 extern int trax_display_summary(unsigned id,
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| D | overlay.h | 2 // $Id$
89 // Returns the current overlay ID. If no overlay is mapped or an overlay
91 // out of overlay (wastes cycles, can end up reading wrong ID on interrupt
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| /hal_xtensa-3.6.0/zephyr/soc/mimx8ml8/xtensa/config/ |
| D | specreg.h | 5 /* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
7 /* Customer ID=12445; Build=0x700c0; Copyright (c) 1998-2002 Tensilica Inc.
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| D | tie.h | 11 Customer ID=12445; Build=0x700c0; Copyright (c) 1999-2017 Cadence Design Systems Inc.
36 #define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
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| /hal_xtensa-3.6.0/zephyr/soc/nxp_imx_adsp/xtensa/config/ |
| D | specreg.h | 5 /* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
7 /* Customer ID=12445; Build=0x700c0; Copyright (c) 1998-2002 Tensilica Inc.
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| D | tie.h | 11 Customer ID=12445; Build=0x700c0; Copyright (c) 1999-2017 Cadence Design Systems Inc.
36 #define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
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| /hal_xtensa-3.6.0/zephyr/soc/mt8195_adsp/xtensa/config/ |
| D | specreg.h | 5 /* $Id: //depot/rel/Homewood/ib.6/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
7 /* Customer ID=15837; Build=0xa1536; Copyright (c) 1998-2002 Tensilica Inc.
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| D | tie.h | 11 Customer ID=15837; Build=0xa1536; Copyright (c) 1999-2022 Cadence Design Systems Inc.
38 #define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
39 #define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
47 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
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| D | secure.h | 4 /* Customer ID=15837; Build=0xa1536; Copyright (c) 2020 Cadence Design Systems, Inc.
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| /hal_xtensa-3.6.0/zephyr/soc/nxp_imx8ulp/xtensa/config/ |
| D | specreg.h | 5 /* $Id: //depot/rel/Foxhill/dot.8/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
7 /* Customer ID=13270; Build=0x92cb6; Copyright (c) 1998-2002 Tensilica Inc.
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| D | tie.h | 11 Customer ID=13270; Build=0x92cb6; Copyright (c) 1999-2021 Cadence Design Systems Inc.
36 #define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
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| /hal_xtensa-3.6.0/src/hal/ |
| D | mp_asm.S | 4 // $Id$
103 Returns the value of the PRID register (processor ID),
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| D | syscache_asm.S | 9 // They should be avoided. (Instead, use xthal_set_[id]cacheattr()
15 // $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/syscache_asm.S#1 $
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| /hal_xtensa-3.6.0/zephyr/soc/dc233c/xtensa/config/ |
| D | tie.h | 36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
37 #define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */
45 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
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| /hal_xtensa-3.6.0/zephyr/soc/intel_icl_adsp/xtensa/config/ |
| D | tie.h | 38 #define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
39 #define XCHAL_CP_MASK 0x03 /* bitmask of all CPs by ID */
47 #define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
52 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
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| /hal_xtensa-3.6.0/zephyr/soc/intel_cnl_adsp/xtensa/config/ |
| D | tie.h | 38 #define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
39 #define XCHAL_CP_MASK 0x03 /* bitmask of all CPs by ID */
47 #define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
52 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
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| /hal_xtensa-3.6.0/zephyr/soc/intel_tgl_adsp/xtensa/config/ |
| D | tie.h | 38 #define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
39 #define XCHAL_CP_MASK 0x03 /* bitmask of all CPs by ID */
47 #define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
52 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
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| /hal_xtensa-3.6.0/.github/workflows/ |
| D | license_check.yml | 12 id: scancode
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| /hal_xtensa-3.6.0/include/machine/ |
| D | xtensa-hal.h | 1 /* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/machine/xtensa-hal.h#1 $ */
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| /hal_xtensa-3.6.0/zephyr/soc/intel_apl_adsp/xtensa/config/ |
| D | tie.h | 38 #define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
39 #define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
47 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
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| /hal_xtensa-3.6.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/ |
| D | tie.h | 38 #define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
39 #define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
47 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
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| /hal_xtensa-3.6.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/ |
| D | tie.h | 38 #define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
39 #define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
47 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
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