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/Zephyr-Core-3.4.0/subsys/tracing/ctf/tsdl/
Dmetadata12 uint8_t id;
27 id = 0x10;
36 id = 0x11;
45 id = 0x12;
56 id = 0x13;
65 id = 0x14;
74 id = 0x15;
83 id = 0x16;
91 id = 0x17;
100 id = 0x18;
[all …]
/Zephyr-Core-3.4.0/drivers/dma/
Ddma_stm32_v1.c20 uint32_t dma_stm32_id_to_stream(uint32_t id) in dma_stm32_id_to_stream() argument
33 __ASSERT_NO_MSG(id < ARRAY_SIZE(stream_nr)); in dma_stm32_id_to_stream()
35 return stream_nr[id]; in dma_stm32_id_to_stream()
58 void dma_stm32_clear_ht(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_clear_ht() argument
71 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in dma_stm32_clear_ht()
73 func[id](DMAx); in dma_stm32_clear_ht()
76 void dma_stm32_clear_tc(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_clear_tc() argument
89 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in dma_stm32_clear_tc()
91 func[id](DMAx); in dma_stm32_clear_tc()
94 bool dma_stm32_is_ht_active(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_is_ht_active() argument
[all …]
Ddma_stm32_v2.c18 uint32_t dma_stm32_id_to_stream(uint32_t id) in dma_stm32_id_to_stream() argument
39 __ASSERT_NO_MSG(id < ARRAY_SIZE(stream_nr)); in dma_stm32_id_to_stream()
41 return stream_nr[id]; in dma_stm32_id_to_stream()
44 void dma_stm32_clear_ht(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_clear_ht() argument
65 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in dma_stm32_clear_ht()
67 func[id](DMAx); in dma_stm32_clear_ht()
70 void dma_stm32_clear_tc(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_clear_tc() argument
91 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in dma_stm32_clear_tc()
93 func[id](DMAx); in dma_stm32_clear_tc()
96 bool dma_stm32_is_ht_active(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_is_ht_active() argument
[all …]
Ddma_stm32.h48 uint32_t dma_stm32_id_to_stream(uint32_t id);
50 uint32_t dma_stm32_slot_to_channel(uint32_t id);
56 bool dma_stm32_is_tc_active(DMA_TypeDef *DMAx, uint32_t id);
57 void dma_stm32_clear_tc(DMA_TypeDef *DMAx, uint32_t id);
58 bool dma_stm32_is_ht_active(DMA_TypeDef *DMAx, uint32_t id);
59 void dma_stm32_clear_ht(DMA_TypeDef *DMAx, uint32_t id);
60 bool dma_stm32_is_te_active(DMA_TypeDef *DMAx, uint32_t id);
61 void dma_stm32_clear_te(DMA_TypeDef *DMAx, uint32_t id);
64 bool dma_stm32_is_dme_active(DMA_TypeDef *DMAx, uint32_t id);
65 void dma_stm32_clear_dme(DMA_TypeDef *DMAx, uint32_t id);
[all …]
Ddma_stm32u5.c46 static void dma_stm32_dump_stream_irq(const struct device *dev, uint32_t id) in dma_stm32_dump_stream_irq() argument
51 stm32_dma_dump_stream_irq(dma, id); in dma_stm32_dump_stream_irq()
54 static void dma_stm32_clear_stream_irq(const struct device *dev, uint32_t id) in dma_stm32_clear_stream_irq() argument
59 dma_stm32_clear_tc(dma, id); in dma_stm32_clear_stream_irq()
60 dma_stm32_clear_ht(dma, id); in dma_stm32_clear_stream_irq()
61 stm32_dma_clear_stream_irq(dma, id); in dma_stm32_clear_stream_irq()
65 uint32_t dma_stm32_id_to_stream(uint32_t id) in dma_stm32_id_to_stream() argument
86 __ASSERT_NO_MSG(id < ARRAY_SIZE(stream_nr)); in dma_stm32_id_to_stream()
88 return stream_nr[id]; in dma_stm32_id_to_stream()
91 bool dma_stm32_is_tc_active(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_is_tc_active() argument
[all …]
Ddma_stm32_bdma.c37 uint32_t bdma_stm32_id_to_channel(uint32_t id) in bdma_stm32_id_to_channel() argument
50 __ASSERT_NO_MSG(id < ARRAY_SIZE(channel_nr)); in bdma_stm32_id_to_channel()
52 return channel_nr[id]; in bdma_stm32_id_to_channel()
75 void bdma_stm32_clear_ht(BDMA_TypeDef *DMAx, uint32_t id) in bdma_stm32_clear_ht() argument
88 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in bdma_stm32_clear_ht()
90 func[id](DMAx); in bdma_stm32_clear_ht()
93 void bdma_stm32_clear_tc(BDMA_TypeDef *DMAx, uint32_t id) in bdma_stm32_clear_tc() argument
106 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in bdma_stm32_clear_tc()
108 func[id](DMAx); in bdma_stm32_clear_tc()
111 bool bdma_stm32_is_ht_active(BDMA_TypeDef *DMAx, uint32_t id) in bdma_stm32_is_ht_active() argument
[all …]
Ddma_stm32_bdma.h49 uint32_t bdma_stm32_id_to_channel(uint32_t id);
51 uint32_t bdma_stm32_slot_to_channel(uint32_t id);
57 bool bdma_stm32_is_gi_active(BDMA_TypeDef *DMAx, uint32_t id);
58 void bdma_stm32_clear_gi(BDMA_TypeDef *DMAx, uint32_t id);
60 void bdma_stm32_clear_tc(BDMA_TypeDef *DMAx, uint32_t id);
61 void bdma_stm32_clear_ht(BDMA_TypeDef *DMAx, uint32_t id);
62 bool bdma_stm32_is_te_active(BDMA_TypeDef *DMAx, uint32_t id);
63 void bdma_stm32_clear_te(BDMA_TypeDef *DMAx, uint32_t id);
65 bool stm32_bdma_is_irq_active(BDMA_TypeDef *dma, uint32_t id);
66 bool stm32_bdma_is_ht_irq_active(BDMA_TypeDef *ma, uint32_t id);
[all …]
/Zephyr-Core-3.4.0/soc/arm/atmel_sam/common/
Dsoc_pmc.c19 void soc_pmc_peripheral_enable(uint32_t id) in soc_pmc_peripheral_enable() argument
21 __ASSERT(id < ID_PERIPH_COUNT, "Invalid peripheral id"); in soc_pmc_peripheral_enable()
23 if (id < 32) { in soc_pmc_peripheral_enable()
24 PMC->PMC_PCER0 = BIT(id); in soc_pmc_peripheral_enable()
26 } else if (id < 64) { in soc_pmc_peripheral_enable()
27 PMC->PMC_PCER1 = BIT(id & 0x1F); in soc_pmc_peripheral_enable()
36 void soc_pmc_peripheral_disable(uint32_t id) in soc_pmc_peripheral_disable() argument
38 __ASSERT(id < ID_PERIPH_COUNT, "Invalid peripheral id"); in soc_pmc_peripheral_disable()
40 if (id < 32) { in soc_pmc_peripheral_disable()
41 PMC->PMC_PCDR0 = BIT(id); in soc_pmc_peripheral_disable()
[all …]
Dsoc_pmc.h19 * @param id peripheral module id, as defined in data sheet.
21 void soc_pmc_peripheral_enable(uint32_t id);
26 * @param id peripheral module id, as defined in data sheet.
28 void soc_pmc_peripheral_disable(uint32_t id);
33 * @param id peripheral module id, as defined in data sheet.
36 uint32_t soc_pmc_peripheral_is_enabled(uint32_t id);
/Zephyr-Core-3.4.0/drivers/reset/
Dreset_stm32.c14 #define STM32_RESET_CLR_OFFSET(id) (((id) >> 17U) & 0xFFFU) argument
15 #define STM32_RESET_SET_OFFSET(id) (((id) >> 5U) & 0xFFFU) argument
16 #define STM32_RESET_REG_BIT(id) ((id)&0x1FU) argument
22 static int reset_stm32_status(const struct device *dev, uint32_t id, in reset_stm32_status() argument
27 *status = !!sys_test_bit(config->base + STM32_RESET_SET_OFFSET(id), in reset_stm32_status()
28 STM32_RESET_REG_BIT(id)); in reset_stm32_status()
33 static int reset_stm32_line_assert(const struct device *dev, uint32_t id) in reset_stm32_line_assert() argument
37 sys_set_bit(config->base + STM32_RESET_SET_OFFSET(id), in reset_stm32_line_assert()
38 STM32_RESET_REG_BIT(id)); in reset_stm32_line_assert()
43 static int reset_stm32_line_deassert(const struct device *dev, uint32_t id) in reset_stm32_line_deassert() argument
[all …]
Dreset_gd32.c14 /** RCU offset (from id field) */
15 #define GD32_RESET_ID_OFFSET(id) (((id) >> 6U) & 0xFFU) argument
16 /** RCU configuration bit (from id field) */
17 #define GD32_RESET_ID_BIT(id) ((id) & 0x1FU) argument
23 static int reset_gd32_status(const struct device *dev, uint32_t id, in reset_gd32_status() argument
28 *status = !!sys_test_bit(config->base + GD32_RESET_ID_OFFSET(id), in reset_gd32_status()
29 GD32_RESET_ID_BIT(id)); in reset_gd32_status()
34 static int reset_gd32_line_assert(const struct device *dev, uint32_t id) in reset_gd32_line_assert() argument
38 sys_set_bit(config->base + GD32_RESET_ID_OFFSET(id), in reset_gd32_line_assert()
39 GD32_RESET_ID_BIT(id)); in reset_gd32_line_assert()
[all …]
Dreset_ast10x0.c33 static int aspeed_reset_line_assert(const struct device *dev, uint32_t id) in aspeed_reset_line_assert() argument
39 if (id >= ASPEED_RESET_GRP_1_OFFSET) { in aspeed_reset_line_assert()
40 id -= ASPEED_RESET_GRP_1_OFFSET; in aspeed_reset_line_assert()
44 return syscon_write_reg(syscon, addr, BIT(id)); in aspeed_reset_line_assert()
47 static int aspeed_reset_line_deassert(const struct device *dev, uint32_t id) in aspeed_reset_line_deassert() argument
53 if (id >= ASPEED_RESET_GRP_1_OFFSET) { in aspeed_reset_line_deassert()
54 id -= ASPEED_RESET_GRP_1_OFFSET; in aspeed_reset_line_deassert()
58 return syscon_write_reg(syscon, addr, BIT(id)); in aspeed_reset_line_deassert()
61 static int aspeed_reset_status(const struct device *dev, uint32_t id, uint8_t *status) in aspeed_reset_status() argument
69 if (id >= ASPEED_RESET_GRP_1_OFFSET) { in aspeed_reset_status()
[all …]
/Zephyr-Core-3.4.0/tests/drivers/can/api/src/
Dcommon.c24 * @brief Standard (11-bit) CAN ID frame 1.
28 .id = TEST_CAN_STD_ID_1,
34 * @brief Standard (11-bit) CAN ID frame 2.
38 .id = TEST_CAN_STD_ID_2,
44 * @brief Extended (29-bit) CAN ID frame 1.
48 .id = TEST_CAN_EXT_ID_1,
54 * @brief Extended (29-bit) CAN ID frame 1.
58 .id = TEST_CAN_EXT_ID_2,
64 * @brief Standard (11-bit) CAN ID RTR frame 1.
68 .id = TEST_CAN_STD_ID_1,
[all …]
Dcommon.h60 * @brief Standard (11-bit) CAN ID frame 1.
65 * @brief Standard (11-bit) CAN ID frame 2.
70 * @brief Extended (29-bit) CAN ID frame 1.
75 * @brief Extended (29-bit) CAN ID frame 1.
80 * @brief Standard (11-bit) CAN ID RTR frame 1.
85 * @brief Extended (29-bit) CAN ID RTR frame 1.
90 * @brief Standard (11-bit) CAN ID frame 1 with CAN-FD payload.
95 * @brief Standard (11-bit) CAN ID frame 2 with CAN-FD payload.
100 * @brief Standard (11-bit) CAN ID filter 1. This filter matches
106 * @brief Standard (11-bit) CAN ID filter 2. This filter matches
[all …]
/Zephyr-Core-3.4.0/samples/subsys/sip_svc/
DREADME.rst39 Got response of transaction id 0x00 and voltage is 0.846878v
40 Got response of transaction id 0x01 and voltage is 0.858170v
41 Got response of transaction id 0x02 and voltage is 0.860168v
42 Got response of transaction id 0x03 and voltage is 0.846832v
43 Got response of transaction id 0x04 and voltage is 0.858337v
44 Got response of transaction id 0x05 and voltage is 0.871704v
45 Got response of transaction id 0x06 and voltage is 0.859421v
46 Got response of transaction id 0x07 and voltage is 0.857254v
47 Got response of transaction id 0x08 and voltage is 0.858429v
48 Got response of transaction id 0x09 and voltage is 0.859879v
[all …]
/Zephyr-Core-3.4.0/subsys/sip_svc/
Dsip_svc_id_mgr.c6 * Arm SiP services service ID manager and ID mapping table force
15 * Create a id key pool using size variable 0..size-1, where we can
16 * track the allocated id.
28 /* Allocate memory for ID pool */ in sip_svc_id_mgr_create()
53 /* Initialize ID */ in sip_svc_id_mgr_create()
58 /* ID pool is full during initialization */ in sip_svc_id_mgr_create()
62 /* Initialize ID in use flags */ in sip_svc_id_mgr_create()
70 /* Delete a created id pool*/
80 /* Retrieve an id from the id pool*/
83 uint32_t id; in sip_svc_id_mgr_alloc() local
[all …]
/Zephyr-Core-3.4.0/subsys/net/lib/lwm2m/
Dlwm2m_obj_access_control.h12 * @brief Main access control logic. Checks if the server with instance id @p server_obj_inst are
13 * allowed to do @p operation on the object instance of object id @p obj_id
14 * and object instance id @p obj_inst_id. If access control is enabled, this should
17 * @param obj_id object id of the object instance having its rights checked.
18 * @param obj_inst_id object instance id of the object instance having its rights checked.
19 * @param server_obj_inst object instance id of the server attempting to do the operation.
34 * @param obj_id object id of the object instance getting an access control.
35 * @param obj_inst_id object instance id of the object instance getting access control.
36 * @param server_obj_inst_id object instance id of the server creating the object instance.
42 * have access to create object instances of object id @p obj_id.
[all …]
/Zephyr-Core-3.4.0/subsys/net/l2/ethernet/lldp/
DKconfig52 # CHASSIS ID TLV CONFIG
55 int "Chassis ID TLV subtype"
59 Chassis ID subtype options are defined below.
74 hex "Chassis ID MAC Address Byte 0"
81 hex "Chassis ID MAC Address Byte 1"
88 hex "Chassis ID MAC Address Byte 2"
95 hex "Chassis ID MAC Address Byte 3"
102 hex "Chassis ID MAC Address Byte 4"
109 hex "Chassis ID MAC Address Byte 5"
117 string "Chassis ID value"
[all …]
/Zephyr-Core-3.4.0/tests/bluetooth/host/id/bt_id_delete/src/
Dmain.c18 #include <host/id.h>
36 * Test deleting an ID, but not the last one
39 * - ID value used is neither corresponds to default index nor the last index
42 * - bt_dev.id_addr[] at index equals to the ID value used is cleared
43 * - bt_dev.irk[] at index equals to the ID value used is cleared (if privacy is enabled)
49 uint8_t id; in ZTEST() local
56 id = 1; in ZTEST()
65 err = bt_id_delete(id); in ZTEST()
70 zassert_true(bt_dev.id_count == id_count, "Incorrect ID count %d was set", bt_dev.id_count); in ZTEST()
72 zassert_mem_equal(&bt_dev.id_addr[id], BT_ADDR_LE_ANY, sizeof(bt_addr_le_t), in ZTEST()
[all …]
Dtest_suite_bt_settings.c18 #include <host/id.h>
23 * Test deleting an ID, but not the last one
28 * - ID value used is neither corresponds to default index nor the last index
33 * - bt_dev.id_addr[] at index equals to the ID value used is cleared
34 * - bt_dev.irk[] at index equals to the ID value used is cleared (if privacy is enabled)
42 uint8_t id; in ZTEST() local
51 id = 1; in ZTEST()
60 err = bt_id_delete(id); in ZTEST()
65 zassert_true(bt_dev.id_count == id_count, "Incorrect ID count %d was set", bt_dev.id_count); in ZTEST()
67 zassert_mem_equal(&bt_dev.id_addr[id], BT_ADDR_LE_ANY, sizeof(bt_addr_le_t), in ZTEST()
[all …]
/Zephyr-Core-3.4.0/dts/bindings/misc/
Dnuvoton,npcx-soc-id.yaml4 description: Nuvoton, NPCX soc ID node
6 compatible: "nuvoton,npcx-soc-id"
9 family-id:
12 description: NPCX family ID
14 chip-id:
17 description: NPCX chip ID
19 device-id:
22 description: NPCX device ID
/Zephyr-Core-3.4.0/subsys/bluetooth/services/
DKconfig.dis47 int "Vendor ID source"
51 The Vendor ID Source field designates which organization assigned the
52 value used in the Vendor ID field value.
54 - 1 Bluetooth SIG, the Vendor ID was assigned by the Bluetooth SIG
55 - 2 USB IF, the Vendor ID was assigned by the USB IF
58 hex "Vendor ID"
62 The Vendor ID field is intended to uniquely identify the vendor of the
63 device. This field is used in conjunction with Vendor ID Source field,
64 which determines which organization assigned the Vendor ID field value.
65 Note: The Bluetooth Special Interest Group assigns Device ID Vendor ID,
[all …]
/Zephyr-Core-3.4.0/doc/build/dts/
Dmacros.bnf26 node-macro =/ %s"DT_N" path-id %s"_EXISTS"
30 node-macro =/ %s"DT_N" path-id %s"_BUS" ["_" dt-name]
32 node-macro =/ %s"DT_N" path-id %s"_REG_NUM"
33 node-macro =/ %s"DT_N" path-id %s"_REG_IDX_" DIGIT "_EXISTS"
34 node-macro =/ %s"DT_N" path-id %s"_REG_IDX_" DIGIT
36 node-macro =/ %s"DT_N" path-id %s"_REG_NAME_" dt-name
39 node-macro =/ %s"DT_N" path-id %s"_IRQ_NUM"
40 node-macro =/ %s"DT_N" path-id %s"_IRQ_IDX_" DIGIT "_EXISTS"
41 node-macro =/ %s"DT_N" path-id %s"_IRQ_IDX_" DIGIT
43 node-macro =/ %s"DT_N" path-id %s"_IRQ_NAME_" dt-name
[all …]
/Zephyr-Core-3.4.0/drivers/display/
Ddisplay_mcux_elcdif.c284 #define MCUX_ELCDIF_PIXEL_BYTES(id) \ argument
285 (DISPLAY_BITS_PER_PIXEL(DT_INST_PROP(id, pixel_format)) / 8)
287 #define MCUX_ELCDIF_DEVICE_INIT(id) \ argument
288 PINCTRL_DT_INST_DEFINE(id); \
289 static void mcux_elcdif_config_func_##id(const struct device *dev); \
290 static uint8_t __aligned(64) frame_buffer_##id[CONFIG_MCUX_ELCDIF_FB_NUM\
291 * DT_INST_PROP(id, width) \
292 * DT_INST_PROP(id, height) \
293 * MCUX_ELCDIF_PIXEL_BYTES(id)]; \
294 static const struct mcux_elcdif_config mcux_elcdif_config_##id = { \
[all …]
/Zephyr-Core-3.4.0/boards/arm/msp_exp432p401r_launchxl/support/
DMSP432P401R.ccxml2 <configurations XML_version="1.2" id="configurations_0">
3 <configuration XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe_0">
4 …ments XDS110 USB Debug Probe_0" href="connections/TIXDS110_Connection.xml" id="Texas Instruments X…
5 <connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe_0">
6 …<instance XML_version="1.2" href="drivers/tixds510cs_dap.xml" id="drivers" xml="tixds510cs_dap.xml…
7 …<instance XML_version="1.2" href="drivers/tixds510cortexM.xml" id="drivers" xml="tixds510cortexM.x…
8 <property Type="choicelist" Value="2" id="SWD Mode Settings">
11 <platform XML_version="1.2" id="platform_0">
12 …<instance XML_version="1.2" desc="MSP432P401R_0" href="devices/msp432p401r.xml" id="MSP432P401R_0"…

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