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/Zephyr-Core-3.5.0/dts/bindings/i3c/
Di3c-controller.yaml3 # SPDX-License-Identifier: Apache-2.0
5 # Fields for I3C Controllers
9 bus: [i3c, i2c]
12 "#address-cells":
16 "#size-cells":
20 i3c-scl-hz:
23 Frequency of the SCL signal used for I3C transfers. When undefined,
24 use the controller default or as specified by the I3C specification.
26 i2c-scl-hz:
29 Frequency of the SCL signal used for I2C transfers. When undefined
Dnxp,mcux-i3c.yaml4 # SPDX-License-Identifier: Apache-2.0
6 description: NXP MCUX I3C controller
8 compatible: "nxp,mcux-i3c"
10 include: [i3c-controller.yaml, pinctrl-device.yaml]
19 i3c-od-scl-hz:
22 Open Drain Frequency for the I3C controller. When undefined, use
23 the controller default or as specified by the I3C specification.
25 clk-divider:
27 description: Main clock divider for I3C
30 clk-divider-tc:
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/Zephyr-Core-3.5.0/samples/sensor/lps22hh_i3c/boards/
Dmimxrt685_evk_cm33.overlay10 i2c-scl-hz = <400000>;
11 i3c-scl-hz = <400000>;
12 i3c-od-scl-hz = <400000>;
14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
/Zephyr-Core-3.5.0/samples/sensor/lsm6dso_i2c_on_i3c/boards/
Dmimxrt685_evk_cm33.overlay10 i2c-scl-hz = <400000>;
11 i3c-scl-hz = <400000>;
12 i3c-od-scl-hz = <400000>;
14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
/Zephyr-Core-3.5.0/tests/drivers/build_all/i3c/boards/
Dqemu_cortex_m3.overlay4 * SPDX-License-Identifier: Apache-2.0
8 i3c0: i3c@88888888 {
9 compatible = "cdns,i3c";
10 #address-cells = <3>;
11 #size-cells = <0>;
13 interrupt-parent = <&nvic>;
15 input-clock-frequency = <200000000>;
16 i3c-scl-hz = <12500000>;
17 i2c-scl-hz = <400000>;
/Zephyr-Core-3.5.0/doc/hardware/peripherals/
Di3c.rst3 Improved Inter-Integrated Circuit (I3C) Bus
6 I3C (Improved Inter-Integrated Circuit) is a two-signal shared
12 Currently, the API is based on `I3C Specification`_ version 1.1.1.
18 .. _i3c-controller-api:
20 I3C Controller API
23 Zephyr's I3C controller API is used when an I3C controller controls
25 This is the most common mode, used to interact with I3C target
28 Due to the nature of the I3C, there are devices on the bus where
30 dynamic address assignment needs to be carried out by the I3C
34 for both I3C and I\ :sup:`2`\ C devices:
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/Zephyr-Core-3.5.0/samples/sensor/lps22hh_i3c/
DREADME.rst3 LPS22HH: Temperature and Pressure Monitor (I3C)
14 This sample uses the LPS22HH sensor controlled using the I3C interface.
16 STEVALMKI192-V1 connected to the I3C header on :ref:`mimxrt685_evk`.
21 - LPS22HH: https://www.st.com/en/mems-and-sensors/lps22hh.html
27 sensor (for example, the one on evaluation board STEVALMKI192-V1).
32 I3C In-Band Interrupt (IBI) to signal new data being available.
33 Since IBI is initiated by the sensor, it will take over the I3C
36 Or else the I3C controller will not be able to be initialized,
43 .. zephyr-app-commands::
44 :zephyr-app: samples/sensor/lps22hh_i3c
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/Zephyr-Core-3.5.0/samples/sensor/lsm6dso_i2c_on_i3c/
DREADME.rst3 LSM6DSO: IMU Sensor Monitor (I2C on I3C bus)
9 12.5Hz and enables a trigger on data ready. It displays on the console
16 exposed by the I3C controller. It has been tested using the LSM6DSO on
17 the evaluation board STEVAL-MKI196V1 connected to the I3C header
23 - LSM6DSO https://www.st.com/en/mems-and-sensors/lsm6dso.html
29 sensor (for example, the one on evaluation board STEVAL-MKI196V1).
34 .. zephyr-app-commands::
35 :zephyr-app: samples/sensor/lsm6dso_i2c_on_i3c
36 :host-os: unix
45 ------------------
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/Zephyr-Core-3.5.0/include/zephyr/drivers/
Di3c.h4 * SPDX-License-Identifier: Apache-2.0
11 * @brief I3C Interface
12 * @defgroup i3c_interface I3C Interface
20 #include <zephyr/drivers/i3c/addresses.h>
21 #include <zephyr/drivers/i3c/ccc.h>
22 #include <zephyr/drivers/i3c/devicetree.h>
23 #include <zephyr/drivers/i3c/ibi.h>
33 * - BCR[7:6]: Device Role
34 * - 0: I3C Target
35 * - 1: I3C Controller capable
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/Zephyr-Core-3.5.0/drivers/i3c/
Di3c_mcux.c6 * SPDX-License-Identifier: Apache-2.0
19 #include <zephyr/drivers/i3c.h>
67 /** Common I3C Driver Config */
87 /** Common I3C Driver Data */
102 * I3C Push-pull mode.
108 * I3C open drain mode.
117 /** I3C open drain clock frequency in Hz. */
146 * @param reg Pointer to 32-bit Register.
156 * @retval -ETIMEDOUT Exhausted all delays without matching.
164 int ret = -ETIMEDOUT; in reg32_poll_timeout()
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/Zephyr-Core-3.5.0/doc/releases/
Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
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