| /Zephyr-latest/dts/arm/xilinx/ |
| D | zynqmp.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-r.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
16 compatible = "xlnx,pinctrl-zynqmp";
19 compatible = "soc-nv-flash";
24 compatible = "mmio-sram";
29 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
31 zephyr,memory-region = "OCM";
40 interrupt-names = "irq_0";
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| D | zynq7000.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-a.dtsi>
8 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
9 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
13 interrupt-parent = <&gic>;
16 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
18 zephyr,memory-region = "OCM_LOW";
22 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
24 zephyr,memory-region = "OCM_HIGH";
28 compatible = "arm,armv8-timer";
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| /Zephyr-latest/dts/bindings/ethernet/ |
| D | xlnx,gem.yaml | 3 # SPDX-License-Identifier: Apache-2.0
10 include: ethernet-controller.yaml
19 clock-frequency:
23 Specifies the base clock frequency from which the GEM's TX clock
25 clock control register in the CRL_APB. The GEM's TX clock frequency
27 which it will be adjusted at run-time. Therefore, the value of this
29 respective GEM's TX clock - by default, this is the IO PLL.
31 mdc-divider:
42 init-mdio-phy:
45 Activates the management of a PHY associated with the controller in-
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | dai.h | 4 * SPDX-License-Identifier: Apache-2.0
48 * clock-related configurations w.r.t the DAI
95 * The type of the DAI. This ID type is used to configure bespoke DAI HW
151 /** TX buffer underrun or RX buffer overrun has occurred. */
164 /** @brief Optional - Pre Start the transmission / reception of data.
166 * Allows the DAI and downstream codecs to prepare for audio Tx/Rx by
174 * first changes the interface state to STOPPING. When the current TX /
188 /** @brief Optional - Post Stop the transmission / reception of data.
191 * Tx/Rx by stopping any required clocks for downstream audio completion.
199 * at first changes the interface state to STOPPING. When all TX blocks
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| D | espi.h | 4 * SPDX-License-Identifier: Apache-2.0
44 *+----------------------------------------------------------------------+
46 *| eSPI controller +-------------+ |
47 *| +-----------+ | Power | +----------+ |
49 *| +------------+ |processor | | controller | | sources | |
50 *| | SPI flash | +-----------+ +-------------+ +----------+ |
52 *| +------------+ | | | |
53 *| | | | +--------+ +---------------+ |
55 *| | | +-----+ +--------+ +----------+ +----v-----+ |
58 *| | | | +--------+ +----------+ +----------+ |
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| /Zephyr-latest/drivers/spi/ |
| D | spi_xec_qmspi_ldma.c | 4 * SPDX-License-Identifier: Apache-2.0
20 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
21 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
35 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
43 /* spin loops waiting for HW to clear soft reset bit */
55 * Overflow TX FIFO
123 return -ETIMEDOUT; in xec_qmspi_spin_yield()
133 * Some QMSPI timing register may be modified by the Boot-ROM OTP
144 taps[0] = regs->TM_TAPS; in qmspi_reset()
145 taps[1] = regs->TM_TAPS_ADJ; in qmspi_reset()
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| /Zephyr-latest/drivers/ethernet/ |
| D | eth_xlnx_gem.c | 5 * SPDX-License-Identifier: Apache-2.0
8 * - Only supports 32-bit addresses in buffer descriptors, therefore
9 * the ZynqMP APU (Cortex-A53 cores) may not be fully supported.
10 * - Hardware timestamps not considered.
11 * - VLAN tags not considered.
12 * - Wake-on-LAN interrupt not supported.
13 * - Send function is not SMP-capable (due to single TX done semaphore).
14 * - Interrupt-driven PHY management not supported - polling only.
15 * - No explicit placement of the DMA memory area(s) in either a
18 * with the Cortex-R5 QEMU target or an actual R5 running without the
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| D | eth_sam_gmac.c | 6 * SPDX-License-Identifier: Apache-2.0
12 * This is a zero-copy networking implementation of an Ethernet driver. To
18 * - one shot PHY setup, no support for PHY disconnect/reconnect
19 * - no statistics collection
67 dcache_enabled = (SCB->CCR & SCB_CCR_DC_Msk); in dcache_is_enabled()
69 static inline void dcache_invalidate(uint32_t addr, uint32_t size) in dcache_invalidate() argument
76 uint32_t start_addr = addr & (uint32_t)~(GMAC_DCACHE_ALIGNMENT - 1); in dcache_invalidate()
77 uint32_t size_full = size + addr - start_addr; in dcache_invalidate()
82 static inline void dcache_clean(uint32_t addr, uint32_t size) in dcache_clean() argument
89 uint32_t start_addr = addr & (uint32_t)~(GMAC_DCACHE_ALIGNMENT - 1); in dcache_clean()
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| D | eth_cyclonev.c | 2 * SPDX-License-Identifier: Apache-2.0
5 * 3504-0 Universal 10/100/1000 Ethernet MAC (DWC_gmac)
9 * https://github.com/altera-opensource/intel-socfpga-hwlib
32 #define INC_WRAP(idx, size) ({ idx = (idx + 1) % size; }) argument
61 /** BBRAM size (Unit:bytes) */
62 int size; member
71 * /us/en/pdfs/literature/hb/cyclone-v/cv_54001.pdf p. 1252
135 sys_write32(tmpreg, EMAC_GMAC_MAC_ADDR_HIGH_ADDR(p->base_addr, n)); in eth_cyclonev_set_mac_addr()
142 sys_write32(tmpreg, EMAC_GMAC_MAC_ADDR_LOW_ADDR(p->base_addr, n)); in eth_cyclonev_set_mac_addr()
156 return -1; in eth_cyclonev_get_software_reset_status()
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| /Zephyr-latest/drivers/ethernet/dwc_xgmac/ |
| D | eth_dwc_xgmac.c | 4 * SPDX-License-Identifier: Apache-2.0
19 #define UPDATE_ETH_STATS_TX_PKT_CNT(dev_data, incr) (dev_data->stats.pkts.tx += incr)
20 #define UPDATE_ETH_STATS_RX_PKT_CNT(dev_data, incr) (dev_data->stats.pkts.rx += incr)
21 #define UPDATE_ETH_STATS_TX_BYTE_CNT(dev_data, incr) (dev_data->stats.bytes.sent += incr)
22 #define UPDATE_ETH_STATS_RX_BYTE_CNT(dev_data, incr) (dev_data->stats.bytes.received += incr)
23 #define UPDATE_ETH_STATS_TX_ERROR_PKT_CNT(dev_data, incr) (dev_data->stats.errors.tx += incr)
24 #define UPDATE_ETH_STATS_RX_ERROR_PKT_CNT(dev_data, incr) (dev_data->stats.errors.rx += incr)
25 #define UPDATE_ETH_STATS_TX_DROP_PKT_CNT(dev_data, incr) (dev_data->stats.tx_dropped += incr)
37 * @brief Run-time device configuration data structure.
40 * controller instance which is modifiable at run-time, such as
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| /Zephyr-latest/drivers/serial/ |
| D | uart_nrfx_uarte.c | 2 * Copyright (c) 2018-2021 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
72 /* Determine if any instance is using asynchronous API with HW byte counting. */
90 /* Driver supports case when all or none instances support that HW feature. */
137 * should be made. More divisions - higher timeout accuracy and processor usage.
141 /* Size of hardware fifo in RX path. */
195 struct uarte_async_tx tx; member
283 (_config->flags & UARTE_CFG_FLAG_LOW_POWER))
296 ((dev->pm_base->flags & BIT(PM_DEVICE_FLAG_ISR_SAFE))), \
311 /* None-zero in case of high speed instances. Baudrate is adjusted by that ratio. */
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| /Zephyr-latest/doc/releases/ |
| D | release-notes-3.6.rst | 12 * New :ref:`GNSS subsystem <gnss_api>` added, enabling geo-awareness in Zephyr applications.
13 * New API and drivers introduced for interfacing with :ref:`keyboard matrices <gpio-kbd>`.
16 * Integrated Trusted Firmware-M (TF-M) 2.0, including an update to Mbed TLS 3.5.2.
19 * Build system now supports Link Time Optimization (LTO), reducing the size of the final image.
23 * Over 30 new supported boards, spanning all Zephyr-supported architectures.
37 * CVE-2023-5779 `Zephyr project bug tracker GHSA-7cmj-963q-jj47
38 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-7cmj-963q-jj47>`_
40 * CVE-2023-6249 `Zephyr project bug tracker GHSA-32f5-3p9h-2rqc
41 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-32f5-3p9h-2rqc>`_
43 * CVE-2023-6749 `Zephyr project bug tracker GHSA-757h-rw37-66hw
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| D | release-notes-3.1.rst | 61 * Split CAN classic and CAN-FD APIs:
90 was moved from Kconfig to :ref:`devicetree <dt-guide>`.
91 See the :dtcompatible:`st,stm32f1-pinctrl` devicetree binding for more information.
182 * MIPI-DSI
184 * Added a :ref:`MIPI-DSI api <mipi_dsi_api>`. This is an experimental API,
196 * Added support for enabling/disabling CAN-FD mode at runtime using :c:macro:`CAN_MODE_FD`.
220 * Added support for Provisioners over PB-GATT
225 * Added support for the full ISO TX data path, including ISOAL
231 * Implemented ISO-AL TX unframed fragmentation
232 * Added support for back-to-back receiving of PDUs on nRF5x platforms
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| D | release-notes-3.2.rst | 13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
157 :dtcompatible:`fixed-partitions`.
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| D | release-notes-4.0.rst | 15 is now the standard way to provide device-specific protection to data at rest. (:github:`76222`)
18 :ref:`ZMS <zms_api>` is a new key-value storage subsystem compatible with all non-volatile storage
25 runtime configuration through vendor specific APIs. Initially the :dtcompatible:`nordic,nrf-comp`,
26 :dtcompatible:`nordic,nrf-lpcomp` and :dtcompatible:`nxp,kinetis-acmp` are supported.
31 Initially implemented drivers include a simple :dtcompatible:`zephyr,gpio-steppers` and a complex
32 sensor-less stall-detection capable with integrated ramp-controller :dtcompatible:`adi,tmc5041`.
50 directory for :zephyr:code-sample-category:`code samples <samples>`.
70 * :cve:`2024-8798`: Under embargo until 2024-11-22
71 * :cve:`2024-10395`: Under embargo until 2025-01-23
72 * :cve:`2024-11263` `Zephyr project bug tracker GHSA-jjf3-7x72-pqm9
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| D | release-notes-3.5.rst | 38 * CVE-2023-3725 `Zephyr project bug tracker GHSA-2g3m-p6c7-8rr3
39 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-2g3m-p6c7-8rr3>`_
41 * CVE-2023-4257 `Zephyr project bug tracker GHSA-853q-q69w-gf5j
42 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-853q-q69w-gf5j>`_
44 * CVE-2023-4258 `Zephyr project bug tracker GHSA-m34c-cp63-rwh7
45 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-m34c-cp63-rwh7>`_
47 * CVE-2023-4259 `Zephyr project bug tracker GHSA-gghm-c696-f4j4
48 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gghm-c696-f4j4>`_
50 * CVE-2023-4260 `Zephyr project bug tracker GHSA-gj27-862r-55wh
51 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gj27-862r-55wh>`_
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| /Zephyr-latest/arch/xtensa/core/startup/ |
| D | reset_vector.S | 3 * SPDX-License-Identifier: Apache-2.0
10 #include <xtensa/xtensa-xer.h>
11 #include <xtensa/xdm-regs.h>
14 #include <xtensa/xtruntime-core-state.h>
42 .size __start, . - __start
46 * Xtensa TX: reset vector segment is only 4 bytes, so must place the
57 #warning "Xtensa TX reset vector not at start of iram0, irom0, or uram0 -- ROMing LSPs may not work"
76 * Even if the processor supports the non-PC-relative L32R option,
77 * it will always start up in PC-relative mode. We take advantage of
78 * this, and use PC-relative mode at least until we're sure the .lit4
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| /Zephyr-latest/drivers/espi/ |
| D | espi_saf_mchp_xec_v2.c | 5 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
27 /* SAF EC Portal read/write flash access limited to 1-64 bytes */
61 * Delay before first Poll-1 command after suspend in 20 ns units
89 /* EC portal local flash r/w buffer */
99 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
107 regs->SAF_CS0_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
109 regs->SAF_CS1_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
117 regs->SAF_CS0_CM_PRF = val; in mchp_saf_cm_prefix_wr()
119 regs->SAF_CS1_CM_PRF = val; in mchp_saf_cm_prefix_wr()
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| /Zephyr-latest/drivers/usb/device/ |
| D | usb_dc_stm32.c | 3 * Copyright (c) 2017, I-SENSE group of ICCS
5 * SPDX-License-Identifier: Apache-2.0
41 * pin(s) in the device tree. E.g: pinctrl-0 = <&usb_otg_fs_vbus_pa9 ...>;
105 * USB BTABLE is stored in the PMA. The size of BTABLE is 4 bytes
130 /* We need n TX IN FIFOs */
133 /* We need a minimum size for RX FIFO - exact number seemingly determined through trial and error */
136 /* Allocate FIFO memory evenly between the TX FIFOs */
137 /* except the first TX endpoint need only 64 bytes */
139 #define TX_FIFO_WORDS (USB_RAM_SIZE / 4 - RX_FIFO_EP_WORDS - TX_FIFO_EP_0_WORDS)
140 /* Number of words for each remaining TX endpoint FIFO */
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| /Zephyr-latest/drivers/dma/ |
| D | dma_iproc_pax_v1.c | 4 * SPDX-License-Identifier: Apache-2.0
33 return ring->pkt_id = 0x0; in reset_pkt_id()
41 ring->pkt_id = (ring->pkt_id + 1) % 32; in alloc_pkt_id()
42 return ring->pkt_id; in alloc_pkt_id()
47 return ring->pkt_id; in curr_pkt_id()
52 return ring->curr.toggle; in curr_toggle_val()
63 r->opq = opq; in rm_write_header_desc()
65 r->bdcount = bdcount; in rm_write_header_desc()
66 r->prot = 0x0; in rm_write_header_desc()
68 r->start = 1; in rm_write_header_desc()
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| D | dma_iproc_pax_v2.c | 4 * SPDX-License-Identifier: Apache-2.0
36 return ring->pkt_id = 0x0; in reset_pkt_id()
41 ring->pkt_id = (ring->pkt_id + 1) % 32; in alloc_pkt_id()
42 return ring->pkt_id; in alloc_pkt_id()
47 return ring->pkt_id; in curr_pkt_id()
52 return ring->curr.toggle; in curr_toggle_val()
64 r->opq = opq; in rm_write_header_desc()
65 r->bdf = 0x0; in rm_write_header_desc()
66 r->res1 = 0x0; in rm_write_header_desc()
68 r->bdcount = bdcount; in rm_write_header_desc()
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| /Zephyr-latest/drivers/usb/udc/ |
| D | udc_stm32.c | 4 * SPDX-License-Identifier: Apache-2.0
78 const struct device *dev = priv->dev; in HAL_PCD_ResetCallback()
79 const struct udc_stm32_config *cfg = dev->config; in HAL_PCD_ResetCallback()
82 /* Re-Enable control endpoints */ in HAL_PCD_ResetCallback()
84 if (ep && ep->stat.enabled) { in HAL_PCD_ResetCallback()
85 HAL_PCD_EP_Open(&priv->pcd, USB_CONTROL_EP_OUT, cfg->ep0_mps, in HAL_PCD_ResetCallback()
90 if (ep && ep->stat.enabled) { in HAL_PCD_ResetCallback()
91 HAL_PCD_EP_Open(&priv->pcd, USB_CONTROL_EP_IN, cfg->ep0_mps, in HAL_PCD_ResetCallback()
95 udc_submit_event(priv->dev, UDC_EVT_RESET, 0); in HAL_PCD_ResetCallback()
102 udc_submit_event(priv->dev, UDC_EVT_VBUS_READY, 0); in HAL_PCD_ConnectCallback()
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| /Zephyr-latest/drivers/i3c/ |
| D | i3c_cdns.c | 4 * SPDX-License-Identifier: Apache-2.0
472 /* Target T_LOW period in open-drain mode. */
484 /* command tx fifo threshold - unused */
486 /* in-band-interrupt data fifo threshold - unused */
488 /* in-band-interrupt response queue threshold */
490 /* tx data threshold - unused */
500 /** Describes peripheral HW configuration determined from CONFx registers. */
510 /* The maximum TX FIFO depth. */
514 /* The maximum DDR TX FIFO depth. */
611 for (i = 15; i >= 0; --i) { in i3c_cdns_crc5()
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| /Zephyr-latest/include/zephyr/net/ |
| D | ieee802154_radio.h | 5 * SPDX-License-Identifier: Apache-2.0
12 * @note All references to the standard in this file cite IEEE 802.15.4-2020.
38 * @details This API provides a common representation of vendor-specific
44 * - a basic, mostly PHY-level driver API to be implemented by all drivers,
45 * - several optional MAC-level extension points to offload performance
51 * offloading to vendor-specific hardware or firmware features may be required
52 * to achieve full compliance with the Thread protocol or IEEE 802.15.4
53 * subprotocols (e.g. fast enough ACK packages, precise timing of timed TX/RX in
56 * Whether or not MAC-level offloading extension points need to be implemented
60 * @note All section, table and figure references are to the IEEE 802.15.4-2020
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| D | ethernet.h | 10 * SPDX-License-Identifier: Apache-2.0
54 uint8_t addr[NET_ETH_ADDR_LEN]; /**< Buffer storing the address */
115 #define NET_ETH_MINIMAL_FRAME_SIZE 60 /**< Minimum Ethernet frame size */
116 #define NET_ETH_MTU 1500 /**< Ethernet MTU size */
128 * Extend the max frame size for DSA (KSZ8794) by one byte (to 1519) to
145 /** TX Checksum offloading supported for all of IPv4, UDP, TCP */
166 /** Changing duplex (half/full) supported */
172 /** IEEE 802.1Qav (credit-based shaping) supported */
205 /** TX-Injection supported */
258 * 10Base-T1S standard.
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