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/Zephyr-latest/dts/bindings/clock/
Dst,stm32-hse-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: STM32 HSE Clock
6 compatible: "st,stm32-hse-clock"
8 include: [fixed-clock.yaml]
11 hse-bypass:
14 HSE crystal oscillator bypass
15 Set to the property to by-pass the oscillator with an external clock.
17 css-enabled:
20 HSE clock security system enabled
21 Set the property to enable the clock security system (CSS) for the HSE clock.
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/
Dclear_clocks.overlay4 * SPDX-License-Identifier: Apache-2.0
14 /delete-property/ hse-bypass;
15 /delete-property/ clock-frequency;
16 /delete-property/ hse-tcxo;
17 /delete-property/ hse-div2;
22 /delete-property/ hsi-div;
26 /delete-property/ div-m;
27 /delete-property/ mul-n;
28 /delete-property/ div-p;
29 /delete-property/ div-q;
[all …]
Dhse_8.overlay4 * SPDX-License-Identifier: Apache-2.0
13 hse-bypass;
14 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
20 clock-frequency = <DT_FREQ_M(8)>;
Dhse_8_bypass.overlay4 * SPDX-License-Identifier: Apache-2.0
13 hse-bypass;
14 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
20 clock-frequency = <DT_FREQ_M(8)>;
Df0_f3_pll_32_hse_8.overlay4 * SPDX-License-Identifier: Apache-2.0
13 hse-bypass;
14 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
27 clock-frequency = <DT_FREQ_M(32)>;
Df1_pll_64_hse_8.overlay4 * SPDX-License-Identifier: Apache-2.0
13 hse-bypass;
14 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
27 clock-frequency = <DT_FREQ_M(64)>;
Dpll_32_hse_8.overlay4 * SPDX-License-Identifier: Apache-2.0
13 hse-bypass;
14 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
27 clock-frequency = <DT_FREQ_M(32)>;
Dclear_f0_f1_f3_clocks.overlay4 * SPDX-License-Identifier: Apache-2.0
14 /delete-property/ hse-bypass;
15 /delete-property/ clock-frequency;
31 /delete-property/ mul;
32 /delete-property/ div;
33 /delete-property/ prediv;
34 /delete-property/ xtpre;
35 /delete-property/ clocks;
40 /delete-property/ clocks;
41 /delete-property/ clock-frequency;
Df2_f4_f7_pll_64_hse_8.overlay4 * SPDX-License-Identifier: Apache-2.0
13 hse-bypass;
14 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
19 div-m = <4>;
20 mul-n = <192>;
21 div-p = <6>;
22 div-q = <8>;
29 clock-frequency = <DT_FREQ_M(64)>;
Dpll_64_hse_8.overlay4 * SPDX-License-Identifier: Apache-2.0
13 hse-bypass;
14 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
19 div-m = <1>;
20 mul-n = <16>;
21 div-q = <2>;
22 div-r = <2>;
29 clock-frequency = <DT_FREQ_M(64)>;
Dclear_f2_f4_f7_clocks.overlay4 * SPDX-License-Identifier: Apache-2.0
14 /delete-property/ hse-bypass;
15 /delete-property/ clock-frequency;
31 /delete-property/ mul-n;
32 /delete-property/ div-m;
33 /delete-property/ div-p;
34 /delete-property/ div-q;
35 /delete-property/ clocks;
40 /delete-property/ clocks;
41 /delete-property/ clock-frequency;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/
Dhse_16.overlay4 * SPDX-License-Identifier: Apache-2.0
13 * Warning: HSE is not implemented on available boards, hence:
19 clock-frequency = <DT_FREQ_M(16)>;
20 hse-bypass;
25 clock-frequency = <DT_FREQ_M(16)>;
26 ahb-prescaler = <1>;
27 apb1-prescaler = <1>;
28 apb2-prescaler = <1>;
29 apb3-prescaler = <1>;
Dpll_hse_160.overlay4 * SPDX-License-Identifier: Apache-2.0
13 * Warning: HSE is not implemented on available boards, hence:
19 clock-frequency = <DT_FREQ_M(16)>;
20 hse-bypass;
24 div-m = <4>;
25 mul-n = <40>;
26 div-q = <2>;
27 div-r = <1>;
34 clock-frequency = <DT_FREQ_M(160)>;
35 ahb-prescaler = <1>;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/
Dhse25.overlay5 * SPDX-License-Identifier: Apache-2.0
14 * Warning: HSE frequency differs on available boards, hence:
19 clock-frequency = <DT_FREQ_M(25)>;
20 hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
26 clock-frequency = <DT_FREQ_M(25)>;
27 ahb-prescaler = <1>;
28 apb1-prescaler = <1>;
29 apb2-prescaler = <1>;
30 apb3-prescaler = <1>;
Dpll_hse25_100.overlay5 * SPDX-License-Identifier: Apache-2.0
14 * Warning: HSE frequency differs on available boards, hence:
19 hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
20 clock-frequency = <DT_FREQ_M(25)>;
25 div-m = <2>;
26 mul-n = <32>;
27 div-p = <4>;
28 div-q = <4>;
29 div-r = <4>;
36 clock-frequency = <DT_FREQ_M(100)>;
[all …]
Dpll_hse25_240.overlay5 * SPDX-License-Identifier: Apache-2.0
14 * Warning: HSE frequency differs on available boards, hence:
19 hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
21 clock-frequency = <DT_FREQ_M(25)>;
25 div-m = <5>;
26 mul-n = <96>;
27 div-p = <2>;
28 div-q = <2>;
29 div-r = <2>;
36 clock-frequency = <DT_FREQ_M(240)>;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Df4_i2s2_pll.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
30 /delete-property/ mul;
31 /delete-property/ div;
32 /delete-property/ prediv;
33 /delete-property/ xtpre;
34 /delete-property/ clocks;
39 /delete-property/ clocks;
40 /delete-property/ clock-frequency;
[all …]
Dwl_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwb_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwb_i2c1_hsi_lptim1_lse.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/
Dcore_init.overlay4 * SPDX-License-Identifier: Apache-2.0
19 /delete-property/ hse-bypass;
20 /delete-property/ clock-frequency;
25 /delete-property/ hsi-div;
41 /delete-property/ div-m;
42 /delete-property/ mul-n;
43 /delete-property/ div-p;
44 /delete-property/ div-q;
45 /delete-property/ div-r;
46 /delete-property/ clocks;
[all …]
Dspi1_per_ck_hse.overlay4 * SPDX-License-Identifier: Apache-2.0
13 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
14 hse-bypass;
24 /delete-property/ clocks;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/
Dhse_8.overlay4 * SPDX-License-Identifier: Apache-2.0
13 hse-bypass;
14 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
20 clock-frequency = <DT_FREQ_M(8)>;
Dpll_hse_96.overlay4 * SPDX-License-Identifier: Apache-2.0
13 hse-bypass;
14 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
19 div-m = <1>;
20 mul-n = <24>;
21 div-p = <2>;
22 div-q = <4>;
23 div-r = <2>;
30 clock-frequency = <DT_FREQ_M(96)>;

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