Searched full:half (Results 1 – 25 of 223) sorted by relevance
123456789
| /Zephyr-Core-3.5.0/dts/bindings/pwm/ |
| D | nxp,imx-pwm.yaml | 40 - "half-cycle"
42 - "half-and-full-cycle"
46 "half-cycle" - registers loaded on a PWM half cycle;
48 "half-and-full-cycle" - registers loaded on a PWM half & full cycle.
|
| /Zephyr-Core-3.5.0/arch/arm/core/ |
| D | Kconfig.vfp | 46 that supports half- and single-precision operations with 16
58 that supports half- and single-precision operations (including fused
81 that supports half-, single- and double-precision operations with 16
94 that supports half-, single- and double-precision operations
108 that supports half-, single-, double-precision operations (including
122 that supports half-, single- and double-precision operations
136 that supports half-, single-, double-precision operations (including
149 half-precision operations (half-precision extension).
|
| /Zephyr-Core-3.5.0/dts/bindings/i3c/ |
| D | i3c-device.yaml | 16 For I3C devices, the 3 fields are static address, first half
17 of Provisioned ID, and the second half of the Provisioned ID.
22 2. First half of the Provisioned ID contains the manufacturer
25 3. Second half of the Provisioned ID contains the combination of
|
| /Zephyr-Core-3.5.0/dts/bindings/ethernet/ |
| D | ethernet-phy.yaml | 23 - "10BASE-T Half-Duplex"
25 - "100BASE-T Half-Duplex"
|
| /Zephyr-Core-3.5.0/include/zephyr/net/ |
| D | mii.h | 85 /** 100BASE-X half duplex capable */
89 /** 10 Mb/s half duplex capable */
93 /** 100BASE-T2 half duplex capable */
132 /** try for 10 Mb/s half duplex support */
141 /** try for 1000BASE-T half duplex support */
151 /** 1000BASE-X half-duplex capable */
155 /** 1000BASE-T half-duplex capable */
|
| /Zephyr-Core-3.5.0/doc/build/dts/ |
| D | bindings.rst | 6 A devicetree on its own is only half the story for describing hardware, as it
8 half.
|
| /Zephyr-Core-3.5.0/samples/boards/stm32/uart/single_wire/ |
| D | README.rst | 5 Use single-wire/half-duplex UART functionality of STM32 devices.
10 A simple application demonstrating how to use the single wire / half-duplex UART
|
| /Zephyr-Core-3.5.0/modules/cmsis-dsp/ |
| D | Kconfig | 65 bool "Half-Precision (16-bit Float) Support"
69 This option enables the half-precision (16-bit) floating-point
|
| /Zephyr-Core-3.5.0/samples/drivers/spi_flash_at45/ |
| D | sample.yaml | 50 - "Writing the first half of the test region... OK"
51 - "Writing the second half of the test region... OK"
|
| /Zephyr-Core-3.5.0/dts/bindings/spi/ |
| D | espressif,esp32-spi.yaml | 17 half-duplex:
20 Enable half-duplex communication mode.
|
| /Zephyr-Core-3.5.0/arch/xtensa/core/ |
| D | xtensa_intgen.py | 50 half = int(len(ints)/2)
53 for i in ints[0:half]:
56 emit_int_handler(ints[0:half])
58 emit_int_handler(ints[half:])
|
| /Zephyr-Core-3.5.0/dts/bindings/dma/ |
| D | st,stm32u5-dma.yaml | 38 0x1: Half-word (16 bits)
43 0x1: Half-word (16 bits)
|
| D | st,stm32-dmamux.yaml | 28 0x1: Half-word (16 bits)
33 0x1: Half-word (16 bits)
|
| D | st,stm32-bdma.yaml | 30 0x1: Half-word (16 bits)
35 0x1: Half-word (16 bits)
|
| D | st,stm32-dma-v2bis.yaml | 33 0x1: STM32_DMA_PERIPH_16BITS: Half-word (16 bits)
38 0x1: STM32_DMA_MEM_16BITS: Half-word (16 bits)
|
| D | st,stm32-dma-v1.yaml | 32 0x1: Half-word (16 bits)
37 0x1: Half-word (16 bits)
|
| /Zephyr-Core-3.5.0/samples/subsys/nvs/boards/ |
| D | nucleo_wb55rg.overlay | 11 /* Set 12KB of storage at the end of 1st half of flash (dual core constraints) */
|
| /Zephyr-Core-3.5.0/dts/bindings/mtd/ |
| D | st,stm32-nv-flash.yaml | 13 description: max erase time(millisecond) of a flash sector or page or half-page
|
| /Zephyr-Core-3.5.0/dts/bindings/serial/ |
| D | espressif,esp32-uart.yaml | 20 Enable the hardware RS485 half duplex mode.
|
| /Zephyr-Core-3.5.0/samples/sensor/ds18b20/boards/ |
| D | nucleo_g0b1re.overlay | 12 * b) the UART TX pin only, while the single wire half-duplex mode is enabled.
|
| /Zephyr-Core-3.5.0/dts/bindings/w1/ |
| D | zephyr,w1-serial.yaml | 7 # the option for a "single-wire Half-duplex" mode, where the TX and RX lines
|
| /Zephyr-Core-3.5.0/drivers/timer/ |
| D | arm_arch_timer.c | 115 * in half the range of a cycle_diff_t for native width divisions in sys_clock_set_timeout()
116 * to be usable elsewhere. Also clamp it to half the range of an in sys_clock_set_timeout()
118 * The half range gives us one bit of extra room to cope with the in sys_clock_set_timeout()
|
| /Zephyr-Core-3.5.0/samples/subsys/fs/littlefs/boards/ |
| D | nucleo_h7a3zi_q.overlay | 29 /* Use second half of flash for the filesystem. */
|
| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/common/include/ |
| D | cpu_init.h | 31 * for each cache way in the bottom half of the L1CCFG register in cpu_early_init()
32 * and poll the top half for them to turn on. in cpu_early_init()
|
| /Zephyr-Core-3.5.0/samples/drivers/misc/grove_display/src/ |
| D | main.c | 74 * First half means incrementally brighter. in main()
75 * Second half is opposite (i.e. goes darker). in main()
|
123456789
