| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | xlnx,xps-gpio-1.00.a.yaml | 1 description: Xilinx AXI GPIO IP node
3 compatible: "xlnx,xps-gpio-1.00.a"
5 include: [gpio-controller.yaml, base.yaml]
7 bus: xlnx,xps-gpio-1.00.a
10 # https://github.com/Xilinx/device-tree-xlnx
16 xlnx,all-inputs:
21 xlnx,all-outputs:
26 xlnx,dout-default:
29 Default output value. If n-th bit is 1, GPIO-n default value is 1.
31 xlnx,gpio-width:
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| /Zephyr-Core-3.5.0/dts/bindings/display/ |
| D | nxp,imx-elcdif.yaml | 1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,imx-elcdif"
8 include: [lcd-controller.yaml, pinctrl-device.yaml]
17 data-bus-width:
19 default: "16-bit"
21 - "16-bit"
22 - "8-bit"
23 - "18-bit"
24 - "24-bit"
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| D | nxp,dcnano-lcdif.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,dcnano-lcdif"
8 include: [lcd-controller.yaml, pinctrl-device.yaml]
17 backlight-gpios:
18 type: phandle-array
21 LCB backlight control gpio. Driver will initialize this GPIO to active high
23 data-bus-width:
25 default: "24-bit"
27 - "16-bit-config1" # 16 bit configuration 1. RGB565: XXXXXXXX_RRRRRGGG_GGGBBBBB
28 - "16-bit-config2" # 16 bit configuration 2. RGB565: XXXRRRRR_XXGGGGGG_XXXBBBBB
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| D | st,stm32-ltdc.yaml | 1 # Copyright (c) 2022, Byte-Lab d.o.o. <dev@byte-lab.com>
2 # SPDX-License-Identifier: Apache-2.0
4 description: STM32 LCD-TFT display controller
6 compatible: "st,stm32-ltdc"
8 include: [lcd-controller.yaml, pinctrl-device.yaml]
11 disp-on-gpios:
12 type: phandle-array
14 Display on/off GPIO pin.
15 Configure the GPIO polarity (active high/active low) according to LCD datasheet.
17 bl-ctrl-gpios:
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| /Zephyr-Core-3.5.0/tests/drivers/build_all/eeprom/ |
| D | app.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 * with real-world devicetree nodes, to allow these tests to run on
15 #address-cells = <1>;
16 #size-cells = <1>;
18 test_gpio: gpio@deadbeef {
19 compatible = "vnd,gpio";
20 gpio-controller;
22 #gpio-cells = <0x2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
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| /Zephyr-Core-3.5.0/drivers/display/ |
| D | display_stm32_ltdc.c | 2 * Copyright (c) 2022 Byte-Lab d.o.o. <dev@byte-lab.com>
5 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/drivers/gpio.h>
81 uint32_t width; member
91 return -ENOTSUP; in stm32_ltdc_blanking_on()
96 return -ENOTSUP; in stm32_ltdc_blanking_off()
101 struct display_stm32_ltdc_data *data = dev->data; in stm32_ltdc_get_framebuffer()
103 return (void *) data->frame_buffer; in stm32_ltdc_get_framebuffer()
109 return -ENOTSUP; in stm32_ltdc_set_brightness()
115 return -ENOTSUP; in stm32_ltdc_set_contrast()
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| D | ssd16xx.c | 3 * Copyright (c) 2018-2020 PHYTEC Messtechnik GmbH
5 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/drivers/gpio.h>
47 /* Width (bits) of integer type representing an x coordinate */
49 /* Width (bits) of integer type representing a y coordinate */
105 uint16_t width; member
114 const struct ssd16xx_config *config = dev->config; in ssd16xx_busy_wait()
115 int pin = gpio_pin_get_dt(&config->busy_gpio); in ssd16xx_busy_wait()
120 pin = gpio_pin_get_dt(&config->busy_gpio); in ssd16xx_busy_wait()
127 const struct ssd16xx_config *config = dev->config; in ssd16xx_write_cmd()
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| D | display_st7789v.c | 9 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/drivers/gpio.h>
48 uint16_t width; member
65 struct st7789v_data *data = dev->data; in st7789v_set_lcd_margins()
67 data->x_offset = x_offset; in st7789v_set_lcd_margins()
68 data->y_offset = y_offset; in st7789v_set_lcd_margins()
74 const struct st7789v_config *config = dev->config; in st7789v_transmit()
80 if (config->cmd_data_gpio.port != NULL) { in st7789v_transmit()
82 gpio_pin_set_dt(&config->cmd_data_gpio, 1); in st7789v_transmit()
83 spi_write_dt(&config->bus, &tx_bufs); in st7789v_transmit()
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| D | uc81xx.c | 5 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/drivers/gpio.h>
80 uint16_t width; member
95 const struct uc81xx_config *config = dev->config; in uc81xx_busy_wait()
96 int pin = gpio_pin_get_dt(&config->busy_gpio); in uc81xx_busy_wait()
101 pin = gpio_pin_get_dt(&config->busy_gpio); in uc81xx_busy_wait()
108 const struct uc81xx_config *config = dev->config; in uc81xx_write_cmd()
115 err = gpio_pin_set_dt(&config->dc_gpio, 1); in uc81xx_write_cmd()
120 err = spi_write_dt(&config->bus, &buf_set); in uc81xx_write_cmd()
129 err = gpio_pin_set_dt(&config->dc_gpio, 0); in uc81xx_write_cmd()
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| D | display_ili9xxx.c | 6 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/display/ili9xxx.h>
27 const struct ili9xxx_config *config = dev->config; in ili9xxx_transmit()
37 gpio_pin_set_dt(&config->cmd_data, ILI9XXX_CMD); in ili9xxx_transmit()
38 r = spi_write_dt(&config->spi, &tx_bufs); in ili9xxx_transmit()
48 gpio_pin_set_dt(&config->cmd_data, ILI9XXX_DATA); in ili9xxx_transmit()
49 r = spi_write_dt(&config->spi, &tx_bufs); in ili9xxx_transmit()
74 const struct ili9xxx_config *config = dev->config; in ili9xxx_hw_reset()
76 if (config->reset.port == NULL) { in ili9xxx_hw_reset()
80 gpio_pin_set_dt(&config->reset, 1); in ili9xxx_hw_reset()
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| D | display_st7735r.c | 7 * Copyright (c) 2020 Kim Bøndergaard <kim@fam-boendergaard.dk>
9 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/drivers/gpio.h>
36 uint16_t width; member
65 struct st7735r_data *data = dev->data; in st7735r_set_lcd_margins()
67 data->x_offset = x_offset; in st7735r_set_lcd_margins()
68 data->y_offset = y_offset; in st7735r_set_lcd_margins()
73 const struct st7735r_config *config = dev->config; in st7735r_set_cmd()
75 gpio_pin_set_dt(&config->cmd_data, is_cmd); in st7735r_set_cmd()
81 const struct st7735r_config *config = dev->config; in st7735r_transmit_hold()
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| /Zephyr-Core-3.5.0/boards/arm/arty/dts/ |
| D | arty_a7_arm_designstart.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 zephyr,shell-uart = &uartlite0;
29 spi-flash0 = &flash0;
33 compatible = "gpio-leds";
105 compatible = "gpio-keys";
149 compatible = "arm,daplink-qspi-mux";
151 interrupt-parent = <&nvic>;
153 mux-gpios = <&daplink_gpio0 0 GPIO_ACTIVE_HIGH>;
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| /Zephyr-Core-3.5.0/dts/bindings/mtd/ |
| D | atmel,at2x-base.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 include: eeprom-base.yaml
15 address-width:
18 description: EEPROM address width in bits
23 wp-gpios:
24 type: phandle-array
26 GPIO to which the write-protect pin of the chip is connected.
28 The device will interpret this signal as active-low.
|
| D | fujitsu,mb85rcxx.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: ["eeprom-base.yaml", i2c-device.yaml]
21 address-width:
24 description: FRAM address width in bits.
26 wp-gpios:
27 type: phandle-array
28 description: GPIO to which the write-protect pin of the chip is connected.
|
| /Zephyr-Core-3.5.0/dts/arm/xilinx/ |
| D | zynqmp.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-r.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
15 compatible = "soc-nv-flash";
20 compatible = "mmio-sram";
25 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
27 zephyr,memory-region = "OCM";
36 interrupt-names = "irq_0";
45 interrupt-names = "irq_0";
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| D | zynq7000.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-a.dtsi>
8 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
9 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
13 interrupt-parent = <&gic>;
16 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
18 zephyr,memory-region = "OCM_LOW";
22 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
24 zephyr,memory-region = "OCM_HIGH";
28 compatible = "arm,armv8-timer";
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| /Zephyr-Core-3.5.0/boards/shields/lmp90100_evb/ |
| D | lmp90100_evb.overlay | 4 * SPDX-License-Identifier: Apache-2.0
13 spi-max-frequency = <1000000>;
15 /* drdyb-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; */
16 #io-channel-cells = <2>;
18 lmp90100_gpio: gpio {
19 compatible = "ti,lmp90xxx-gpio";
20 gpio-controller;
23 #gpio-cells = <2>;
36 address-width = <8>;
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| /Zephyr-Core-3.5.0/tests/drivers/build_all/display/ |
| D | app.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 * with real-world devicetree nodes, to allow these tests to run on
15 #address-cells = <1>;
16 #size-cells = <1>;
18 test_gpio: gpio@deadbeef {
19 compatible = "vnd,gpio";
20 gpio-controller;
22 #gpio-cells = <0x2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
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| /Zephyr-Core-3.5.0/boards/arm/reel_board/ |
| D | reel_board.dts | 2 * Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH
5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
11 #include "reel_board-pinctrl.dtsi"
19 zephyr,shell-uart = &uart0;
20 zephyr,uart-mcumgr = &uart0;
21 zephyr,bt-mon-uart = &uart0;
22 zephyr,bt-c2h-uart = &uart0;
25 zephyr,code-partition = &slot0_partition;
30 compatible = "gpio-leds";
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| /Zephyr-Core-3.5.0/boards/arm/cyclonev_socdk/ |
| D | cyclonev_socdk.dts | 2 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga";
28 eeprom-0 = &eeprom;
32 compatible = "gpio-leds";
50 local-mac-address = [e6 88 2d 82 1f d4];
52 gpio0: gpio@ff708000 {
55 gpio1: gpio@ff709000 {
58 gpio2: gpio@ff70a000 {
70 address-width = <8>;
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| /Zephyr-Core-3.5.0/boards/arm/atsamd21_xpro/doc/ |
| D | index.rst | 10 prototyping with the SAM D21 Cortex®-M0+ processor-based
16 :width: 500px
18 :alt: ATSAMD21-XPRO
20 ATSAMD21-XPRO (Credit: `Microchip Technology`_)
25 - ATSAMD21J18 ARM Cortex-M0+ processor at 48 MHz
26 - 32.768 kHz crystal oscillator
27 - 256 KiB flash memory and 32 KiB of RAM
28 - One yellow user LED
29 - One mechanical user push button
30 - One reset button
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| /Zephyr-Core-3.5.0/dts/arm/nordic/ |
| D | nrf5340_cpunet.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
13 zephyr,flash-controller = &flash_controller;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-m33";
24 #address-cells = <1>;
25 #size-cells = <1>;
28 compatible = "arm,armv8m-mpu";
36 compatible = "nordic,nrf-ficr";
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| D | nrf52840.dtsi | 1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
9 zephyr,flash-controller = &flash_controller;
13 #address-cells = <1>;
14 #size-cells = <0>;
18 compatible = "arm,cortex-m4f";
20 #address-cells = <1>;
21 #size-cells = <1>;
24 compatible = "arm,armv7m-itm";
26 swo-ref-frequency = <32000000>;
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| /Zephyr-Core-3.5.0/dts/riscv/sifive/ |
| D | riscv32-fe310.dtsi | 1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <zephyr/dt-bindings/gpio/gpio.h>
4 #include <zephyr/dt-bindings/pwm/pwm.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "sifive,FE310G-0002-Z0-dev", "fe310-dev", "sifive-dev";
11 model = "SiFive,FE310G-0002-Z0";
13 coreclk: core-clk {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
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| /Zephyr-Core-3.5.0/dts/bindings/input/ |
| D | st,stmpe811.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: i2c-device.yaml
11 int-gpios:
12 type: phandle-array
14 Interrupt GPIO. Used by the controller to signal touch data is
17 screen-width:
21 Screen width for scaling the reported coordinates.
24 screen-height:
31 raw-x-min:
37 raw-y-min:
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