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/Zephyr-Core-3.5.0/dts/bindings/gpio/
Dintel,gpio.yaml1 # Copyright (c) 2018-2019 Intel Corporation
2 # SPDX-License-Identifier: Apache-2.0
4 description: Intel GPIO node
6 compatible: "intel,gpio"
8 include: [gpio-controller.yaml, base.yaml]
14 group-index:
16 description: Group number for this GPIO entry
23 description: Number of pins for this GPIO entry
25 pin-offset:
28 description: Pin offset of this GPIO entry
[all …]
/Zephyr-Core-3.5.0/dts/x86/intel/
Delkhart_lake.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,elkhart-lake";
20 d-cache-line-size = <64>;
38 #address-cells = <1>;
39 #interrupt-cells = <3>;
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Draptor_lake.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/pcie/pcie.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,raptor-lake";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
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Dalder_lake.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "intel,alder-lake";
21 d-cache-line-size = <64>;
34 #address-cells = <1>;
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/Zephyr-Core-3.5.0/drivers/interrupt_controller/
Dintc_miwu.c4 * SPDX-License-Identifier: Apache-2.0
13 * The device Multi-Input Wake-Up Unit (MIWU) supports the Nuvoton embedded
19 * wake-up input (WUI) sources.
24 * 1. npcxn-miwus-wui-map.dtsi: it presents relationship between wake-up inputs
25 * (WUI) and its source device such as gpio, timer, eSPI VWs and so on.
26 * 2. npcxn-miwus-int-map.dtsi: it presents relationship between MIWU group
27 * and NVIC interrupt in npcx series. Please notice it isn't 1-to-1 mapping.
28 * For example, here is the mapping between miwu0's group a & d and IRQ7:
41 * 0x09, the driver checks the pending bits of group a and group d in ISR.
54 #include <zephyr/drivers/gpio.h>
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/Zephyr-Core-3.5.0/dts/bindings/led/
Dgpio-leds.yaml2 # SPDX-License-Identifier: Apache-2.0
5 This allows you to define a group of LEDs. Each LED in the group is
6 controlled by a GPIO. Each LED is defined in a child node of the
7 gpio-leds node.
13 compatible = "gpio-leds";
28 - led_0 is pin 1 on gpio0. The LED is on when the pin is low,
30 - led_1 is pin 2 on gpio0. The LED is on when the pin is high,
32 - led_2 is pin 15 on gpio1. The LED is on when the pin is low,
33 and the pin's internal pull-up resistor should be enabled.
35 compatible: "gpio-leds"
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/Zephyr-Core-3.5.0/dts/bindings/pinctrl/
Dite,it8xxx2-pinctrl-func.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func3-ext:
21 the setting of func3-gcr, some pins require external setting.
23 func3-ext-mask:
26 func4-gcr:
29 func4-en-mask:
32 volt-sel:
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Dnxp,s32ze-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
9 the SoC's devicetree, will define pin configurations in pin groups. Each group
11 and each numbered subgroup in the pin group defines all the pins for that
13 a group selects the pins to be configured, and the remaining properties set
20 #include <nxp/s32/S32Z27-BGA594-pinctrl.h>
26 output-enable;
30 input-enable;
39 In addition to 'pinmux' property, each group can contain other properties such as
40 'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
41 'pinmux' array. To enable the input buffer use 'input-enable' and to enable the
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/Zephyr-Core-3.5.0/dts/riscv/ite/
Dit8xxx2-wuc-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/dt-util.h>
11 it8xxx2-wuc-map {
12 compatible = "ite,it8xxx2-wuc-map";
14 /* WUC group 2 */
34 /* WUC group 3 */
60 /* WUC group 4 */
74 /* WUC group 5 */
100 /* WUC group 6 */
126 /* WUC group 7 */
[all …]
Dit81xx2.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 gpiogcr: gpio-gcr@f01600 {
12 compatible = "ite,it8xxx2-gpiogcr";
17 compatible = "ite,it8xxx2-gpiokscan";
23 reg-names = "goen", "gctrl", "gdat", "gdmr", "gpod";
25 gpio-controller;
26 #gpio-cells = <2>;
30 compatible = "ite,it8xxx2-gpiokscan";
36 reg-names = "goen", "gctrl", "gdat", "gdmr", "gpod";
38 gpio-controller;
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Dit82xx2.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 compatible = "mmio-sram";
16 intc: interrupt-controller@f03f00 {
17 compatible = "ite,it8xxx2-intc-v2";
18 #address-cells = <0>;
19 #interrupt-cells = <2>;
20 interrupt-controller;
25 compatible = "ite,it8xxx2-watchdog";
29 interrupt-parent = <&intc>;
32 gpiogcr: gpio-gcr@f03e00 {
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/Zephyr-Core-3.5.0/soc/arm/nuvoton_npcx/common/
Dscfg.c4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/drivers/gpio.h>
9 #include <zephyr/dt-bindings/pinctrl/npcx-pinctrl.h>
28 * GPIO in pin-mux init function.
30 * def-io-conf-list {
37 .group = DT_PHA(DT_PROP_BY_IDX(node_id, prop, idx), alts, group), \
58 /* Pin-control local functions */
62 uint8_t alt_mask = BIT(alt->bit); in npcx_pinctrl_alt_sel()
65 * alt_fun == 0 means select GPIO, otherwise Alternate Func. in npcx_pinctrl_alt_sel()
71 if (!!alt_func != !!alt->inverted) { in npcx_pinctrl_alt_sel()
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Dsoc_miwu.h4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/drivers/gpio.h>
60 * @brief NPCX wake-up input source structure
62 * Used to indicate a Wake-Up Input source (WUI) belongs to which group and bit
63 * of Multi-Input Wake-Up Unit (MIWU) modules.
67 uint8_t group:3; /** A source belongs to which group of MIWU table. */ member
68 uint8_t bit:3; /** A source belongs to which bit of MIWU group. */
72 * Define npcx miwu driver callback handler signature for wake-up input source
80 * @brief MIWU/GPIO information structure
82 * It contains both GPIO and MIWU information which is stored in unused field
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/Zephyr-Core-3.5.0/dts/bindings/input/
Dgpio-keys.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Zephyr Input GPIO KEYS parent node
7 This defines a group of buttons that can generate input events. Each button
8 is defined in a child node of the gpio-keys node and defines a specific key
13 #include <zephyr/dt-bindings/input/input-event-codes.h>
17 compatible = "gpio-keys";
26 compatible: "gpio-keys"
31 debounce-interval-ms:
38 child-binding:
39 description: GPIO KEYS child node
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/Zephyr-Core-3.5.0/drivers/pinctrl/
Dpinctrl_npcx.c4 * SPDX-License-Identifier: Apache-2.0
38 /* Pin-control local functions for peripheral devices */
39 static bool npcx_periph_pinmux_has_lock(int group) in npcx_periph_pinmux_has_lock() argument
42 if (group == 0x00 || (group >= 0x02 && group <= 0x04) || group == 0x06 || in npcx_periph_pinmux_has_lock()
43 group == 0x0b || group == 0x0f) { in npcx_periph_pinmux_has_lock()
47 if (group == 0x00 || (group >= 0x02 && group <= 0x06) || group == 0x0b || in npcx_periph_pinmux_has_lock()
48 group == 0x0d || (group >= 0x0f && group <= 0x12)) { in npcx_periph_pinmux_has_lock()
59 uint8_t alt_mask = BIT(alt->bit); in npcx_periph_pinmux_configure()
62 * is_alternate == 0 means select GPIO, otherwise Alternate Func. in npcx_periph_pinmux_configure()
68 if (is_alternate != alt->inverted) { in npcx_periph_pinmux_configure()
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/Zephyr-Core-3.5.0/doc/build/dts/
Dphandles.rst1 .. _dt-phandles:
19 .. code-block:: DTS
22 lbl_a: node-1 {};
23 lbl_b: lbl_c: node-2 {};
28 - ``/node-1`` as ``&lbl_a``
29 - ``/node-2`` as either ``&lbl_b`` or ``&lbl_c``
40 :ref:`dt-bindings-properties` in the devicetree bindings documentation.
47 You can use phandles to refer to ``node-b`` from ``node-a``, where ``node-b``
48 is related to ``node-a`` in some way.
50 One common example is when ``node-a`` represents some hardware that
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/Zephyr-Core-3.5.0/dts/bindings/i2c/
Dst,stm32-i2c-v1.yaml1 # Copyright (c) 2017 I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32-i2c-v1"
8 include: [i2c-controller.yaml, pinctrl-device.yaml]
17 pinctrl-0:
20 pinctrl-names:
23 scl-gpios:
24 type: phandle-array
26 GPIO to which the I2C SCL signal is routed. This is only needed for
29 sda-gpios:
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Dst,stm32-i2c-v2.yaml1 # Copyright (c) 2017 I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32-i2c-v2"
8 include: [i2c-controller.yaml, pinctrl-device.yaml]
17 pinctrl-0:
20 pinctrl-names:
26 An optional table of pre-computed i2c timing values with the
29 Precise timings values for a given Hardware can be pre-computed
38 clock-frequency timing>
47 scl-gpios:
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/Zephyr-Core-3.5.0/dts/bindings/spi/
Dspi-controller.yaml1 # Copyright (c) 2018, I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
11 clock-frequency:
15 "#address-cells":
18 "#size-cells":
21 cs-gpios:
22 type: phandle-array
25 in the array specifies a GPIO. The index in the array
26 corresponds to the child node that the CS gpio controls.
31 cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
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/Zephyr-Core-3.5.0/dts/xtensa/espressif/esp32s2/
Desp32s2_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/clock/esp32s2_clock.h>
12 #include <zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h>
13 #include <dt-bindings/pinctrl/esp32-pinctrl.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
20 die-temp0 = &coretemp;
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/Zephyr-Core-3.5.0/dts/bindings/regulator/
Dregulator-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GPIO-controlled voltage of regulators
8 vccq_sd0: regulator-vccq-sd0 {
9 compatible = "regulator-gpio";
11 regulator-name = "SD0 VccQ";
12 regulator-min-microvolt = <1800000>;
13 regulator-max-microvolt = <3300000>;
15 enable-gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
20 regulator-boot-on;
23 In the above example, three GPIO pins are used for controlling the regulator:
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/Zephyr-Core-3.5.0/include/zephyr/drivers/misc/pio_rpi_pico/
Dpio_rpi_pico.h6 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/devicetree/gpio.h>
34 .origin = -1, \
59 * @brief Get a pin number from a pinctrl / group name and index
72 * input-enable;
82 * pinctrl-0 = <&pio_child_default>;
83 * pinctrl-names = "default";
99 * @param g_name group name
100 * @param g_idx group index
108 * @brief Get a pin number from a pinctrl / group name and index
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/Zephyr-Core-3.5.0/dts/bindings/usb/
Dusb-controller.yaml1 # Copyright (c) 2018, I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
11 maximum-speed:
14 speed. Valid arguments are "super-speed", "high-speed",
15 "full-speed" and "low-speed". If this is not passed
19 - "low-speed"
20 - "full-speed"
21 - "high-speed"
22 - "super-speed"
24 vbus-gpios:
[all …]
/Zephyr-Core-3.5.0/dts/xtensa/espressif/esp32/
Desp32_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/clock/esp32_clock.h>
12 #include <zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h>
13 #include <dt-bindings/pinctrl/esp32-pinctrl.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
20 zephyr,flash-controller = &flash;
24 #address-cells = <1>;
[all …]
/Zephyr-Core-3.5.0/dts/xtensa/espressif/esp32s3/
Desp32s3_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/clock/esp32s3_clock.h>
12 #include <zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h>
13 #include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
19 zephyr,flash-controller = &flash;
23 #address-cells = <1>;
24 #size-cells = <0>;
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