Searched +full:gen0 +full:- +full:assert (Results 1 – 5 of 5) sorted by relevance
| /Zephyr-Core-3.5.0/dts/bindings/pwm/ |
| D | xlnx,xps-timer-1.00.a-pwm.yaml | 3 compatible: "xlnx,xps-timer-1.00.a-pwm"
5 include: ["xlnx,xps-timer-1.00.a.yaml", pwm-controller.yaml]
8 xlnx,gen0-assert:
11 xlnx,gen1-assert:
14 xlnx,trig0-assert:
17 xlnx,trig1-assert:
20 pwm-cells:
21 - channel
23 - period
24 - flags
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| /Zephyr-Core-3.5.0/tests/drivers/build_all/pwm/boards/ |
| D | arty_a7_arm_designstart_m1.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "xlnx,xps-timer-1.00.a-pwm";
11 interrupt-parent = <&nvic>;
13 clock-frequency = <100000000>;
14 xlnx,count-width = <0x20>;
15 xlnx,gen0-assert = <0x1>;
16 xlnx,gen1-assert = <0x1>;
17 xlnx,one-timer-only = <0x0>;
18 xlnx,trig0-assert = <0x1>;
19 xlnx,trig1-assert = <0x0>;
[all …]
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| /Zephyr-Core-3.5.0/tests/drivers/build_all/counter/boards/ |
| D | arty_a7_arm_designstart_m1.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "xlnx,xps-timer-1.00.a";
11 interrupt-parent = <&nvic>;
13 clock-frequency = <100000000>;
14 xlnx,count-width = <0x20>;
15 xlnx,gen0-assert = <0x1>;
16 xlnx,gen1-assert = <0x1>;
17 xlnx,one-timer-only = <0x0>;
18 xlnx,trig0-assert = <0x1>;
19 xlnx,trig1-assert = <0x1>;
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| /Zephyr-Core-3.5.0/dts/bindings/rtc/ |
| D | xlnx,xps-timer-1.00.a.yaml | 3 compatible: "xlnx,xps-timer-1.00.a"
8 # https://github.com/Xilinx/meta-xilinx
11 clock-frequency:
14 xlnx,count-width:
18 - 8
19 - 16
20 - 32
24 xlnx,gen0-assert:
27 - 0
28 - 1
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| /Zephyr-Core-3.5.0/drivers/pwm/ |
| D | pwm_xlnx_axi_timer.c | 4 * SPDX-License-Identifier: Apache-2.0
39 /* Generate PWM mode, count-down, auto-reload */
51 const struct xlnx_axi_timer_config *config = dev->config; in xlnx_axi_timer_read32()
53 return sys_read32(config->base + offset); in xlnx_axi_timer_read32()
60 const struct xlnx_axi_timer_config *config = dev->config; in xlnx_axi_timer_write32()
62 sys_write32(value, config->base + offset); in xlnx_axi_timer_write32()
69 const struct xlnx_axi_timer_config *config = dev->config; in xlnx_axi_timer_set_cycles()
76 return -ENOTSUP; in xlnx_axi_timer_set_cycles()
102 return -ENOTSUP; in xlnx_axi_timer_set_cycles()
106 tlr0 = period_cycles - 2; in xlnx_axi_timer_set_cycles()
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