Searched full:frequencies (Results 1 – 25 of 62) sorted by relevance
123
| /Zephyr-Core-3.6.0/include/zephyr/dt-bindings/clock/ |
| D | esp32c3_clock.h | 16 /* Supported CPU Frequencies */
20 /* Supported XTAL Frequencies */
24 /* Supported RTC fast clock frequencies */
28 /* Supported RTC slow clock frequencies */
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| D | esp32s2_clock.h | 16 /* Supported CPU Frequencies */
23 /* Supported XTAL Frequencies */
26 /* Supported RTC fast clock frequencies */
30 /* Supported RTC slow clock frequencies */
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| D | esp32_clock.h | 17 /* Supported CPU Frequencies */
24 /* Supported XTAL Frequencies */
30 /* Supported RTC fast clock frequencies */
33 /* Supported RTC slow clock frequencies */
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| D | esp32s3_clock.h | 16 /* Supported CPU Frequencies */
23 /* Supported XTAL Frequencies */
29 /* Supported RTC fast clock frequencies */
32 /* Supported RTC slow clock frequencies */
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| /Zephyr-Core-3.6.0/dts/bindings/usb/uac2/ |
| D | zephyr,uac2-clock-source.yaml | 48 sampling-frequencies:
52 Sampling Frequencies, in Hz, this Clock Source Entity can generate.
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| /Zephyr-Core-3.6.0/dts/bindings/timer/ |
| D | nxp,imx-gpt.yaml | 20 description: gpt frequencies
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| /Zephyr-Core-3.6.0/soc/arm/atmel_sam/sam4e/ |
| D | soc.c | 64 * hurt lower clock frequencies. However, a high frequency with too in clock_init()
66 * is the safe setting for all of this SoCs usable frequencies. in clock_init()
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| /Zephyr-Core-3.6.0/tests/kernel/timer/cycle64/ |
| D | testcase.yaml | 10 # As other platforms are added with varying timer frequencies, increase
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| /Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/ |
| D | spi1_pllq_2_d1ppre_4.overlay | 13 * APB2 and PLL_Q clock frequencies are equal.
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| /Zephyr-Core-3.6.0/soc/arm/atmel_sam/sam4s/ |
| D | soc.c | 67 * hurt lower clock frequencies. However, a high frequency with too in clock_init()
69 * is the safe setting for all of this SoCs usable frequencies. in clock_init()
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| /Zephyr-Core-3.6.0/dts/bindings/sensor/ |
| D | ti,fdc2x1x.yaml | 233 1 = divide by 1. Choose for sensor frequencies between
235 2 = divide by 2. Choose for sensor frequencies between 5MHz
239 2 = divide by 2. Choose for sensor frequencies between
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| /Zephyr-Core-3.6.0/samples/subsys/usb/uac2_explicit_feedback/ |
| D | app.overlay | 19 sampling-frequencies = <48000>;
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| /Zephyr-Core-3.6.0/tests/drivers/sdhc/ |
| D | README.txt | 16 * Set_IO test: Verify that the SDHC will reject clock frequencies outside of
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| /Zephyr-Core-3.6.0/dts/bindings/clock/ |
| D | nordic,nrf-hsfll.yaml | 7 The HSFLL mixed-mode IP generates several clock frequencies in the range from
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| /Zephyr-Core-3.6.0/subsys/usb/device_next/class/ |
| D | usbd_uac2.c | 72 const uint8_t id, const uint32_t **frequencies);
499 const uint32_t *frequencies; in get_clock_source_request() local
510 count = clock_frequencies(node, CONTROL_ENTITY_ID(setup), &frequencies); in get_clock_source_request()
516 frequencies[0]); in get_clock_source_request()
524 layout3_range_response(buf, setup->wLength, frequencies, in get_clock_source_request()
525 frequencies, NULL, count); in get_clock_source_request()
772 const uint8_t id, const uint32_t **frequencies) in DT_INST_FOREACH_STATUS_OKAY()
780 *frequencies = FREQUENCY_TABLE_NAME(node, i); \
790 *frequencies = NULL; \
795 *frequencies = NULL;
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| /Zephyr-Core-3.6.0/soc/arm/arm/beetle/ |
| D | soc_pll.h | 50 /* BEETLE PLL Supported Frequencies */
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| /Zephyr-Core-3.6.0/soc/arm/quicklogic_eos_s3/ |
| D | soc.h | 13 /* Available frequencies */
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| /Zephyr-Core-3.6.0/dts/bindings/spi/ |
| D | espressif,esp32-spi.yaml | 63 possible the use of operating frequencies higher than 20 MHz.
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| D | microchip,xec-qmspi-ldma.yaml | 85 Allows different frequencies for CS#0 and CS1# devices. This applies
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| /Zephyr-Core-3.6.0/soc/arm/microchip_mec/common/reg/ |
| D | mec_pwm.h | 57 /* PWM input frequencies selected in configuration register. */
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| /Zephyr-Core-3.6.0/tests/subsys/usb/uac2/ |
| D | app.overlay | 19 sampling-frequencies = <48000>;
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| /Zephyr-Core-3.6.0/drivers/sensor/bmi08x/ |
| D | bmi08x.c | 12 * Output data rate map with allowed frequencies:
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| /Zephyr-Core-3.6.0/soc/riscv/sifive_freedom/e300/ |
| D | clock.c | 21 * peripheral clock). This code supports the following frequencies: in fe310_clock_init()
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| /Zephyr-Core-3.6.0/soc/riscv/espressif_esp32/esp32c3/ |
| D | Kconfig.soc | 70 startup, and approximate clock frequencies will be assumed:
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| /Zephyr-Core-3.6.0/doc/build/dts/ |
| D | dt-vs-kconfig.rst | 13 Examples include peripherals on a board, boot-time clock frequencies,
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