| /hal_nxp-latest/mcux/mcux-sdk/components/clock/porting/platform/imx95/ |
| D | hal_clock_platform.h | 28 /* unify clock id for clock sources and ips */
29 /* clock id for clock sources */
30 hal_clock_ext = 0, /* clock id for EXT_CLK */
31 hal_clock_osc32k = 1, /* clock id for OSC_32K_CLK */
32 hal_clock_osc24m = 2, /* clock id for OSC_24M_CLK */
33 hal_clock_fro = 3, /* clock id for FRO_CLK */
34 hal_clock_syspll1ctl = 4, /* clock id for SYS_PLL1_CTL */
35 hal_clock_syspll1dfs0ctl = 5, /* clock id for SYS_PLL1_DFS0_CTL */
36 hal_clock_syspll1dfs0 = 6, /* clock id for SYS_PLL1_DFS0_CLK */
37 hal_clock_syspll1dfs0div2 = 7, /* clock id for SYS_PLL1_DFS0_DIV2_CLK */
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1171/ |
| D | fsl_pm_device.h | 53 kResc_CPU_PLATFORM = 0U, /*!< CPU platform, this resource is suitable for CM7 and CM4. */
97 kResc_FBB_M7 = 38U, /*!< Forward body biasing for CM7 platform. */
98 kResc_RBB_SOC = 39U, /*!< Reverse body biasing for Soc
100 kResc_RBB_LPSR = 40U, /*!< Reverse body biasing for LPSR power domain. */
114 …urce constraints definition of CPU platform (suitable for CM7 and CM4 processors), with support fo…
130 * @brief Resource constraints definition of OSC_RC_16M, with support for 2 modes:
138 * @brief Resource constraints definition of OSC_RC_48M, with support for 2 modes:
146 * @brief Resource constraints definition of OSC_RC_48M_DIV2, with support for 2 modes:
154 * @brief Resource constraints definition of OSC_RC_400M, with support for 2 modes:
162 * @brief Resource constraints definition of OSC_RC_24M, with support for 2 modes:
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1172/ |
| D | fsl_pm_device.h | 53 kResc_CPU_PLATFORM = 0U, /*!< CPU platform, this resource is suitable for CM7 and CM4. */
97 kResc_FBB_M7 = 38U, /*!< Forward body biasing for CM7 platform. */
98 kResc_RBB_SOC = 39U, /*!< Reverse body biasing for Soc
100 kResc_RBB_LPSR = 40U, /*!< Reverse body biasing for LPSR power domain. */
114 …urce constraints definition of CPU platform (suitable for CM7 and CM4 processors), with support fo…
130 * @brief Resource constraints definition of OSC_RC_16M, with support for 2 modes:
138 * @brief Resource constraints definition of OSC_RC_48M, with support for 2 modes:
146 * @brief Resource constraints definition of OSC_RC_48M_DIV2, with support for 2 modes:
154 * @brief Resource constraints definition of OSC_RC_400M, with support for 2 modes:
162 * @brief Resource constraints definition of OSC_RC_24M, with support for 2 modes:
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1173/ |
| D | fsl_pm_device.h | 53 kResc_CPU_PLATFORM = 0U, /*!< CPU platform, this resource is suitable for CM7 and CM4. */
97 kResc_FBB_M7 = 38U, /*!< Forward body biasing for CM7 platform. */
98 kResc_RBB_SOC = 39U, /*!< Reverse body biasing for Soc
100 kResc_RBB_LPSR = 40U, /*!< Reverse body biasing for LPSR power domain. */
114 …urce constraints definition of CPU platform (suitable for CM7 and CM4 processors), with support fo…
130 * @brief Resource constraints definition of OSC_RC_16M, with support for 2 modes:
138 * @brief Resource constraints definition of OSC_RC_48M, with support for 2 modes:
146 * @brief Resource constraints definition of OSC_RC_48M_DIV2, with support for 2 modes:
154 * @brief Resource constraints definition of OSC_RC_400M, with support for 2 modes:
162 * @brief Resource constraints definition of OSC_RC_24M, with support for 2 modes:
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1176/ |
| D | fsl_pm_device.h | 53 kResc_CPU_PLATFORM = 0U, /*!< CPU platform, this resource is suitable for CM7 and CM4. */
97 kResc_FBB_M7 = 38U, /*!< Forward body biasing for CM7 platform. */
98 kResc_RBB_SOC = 39U, /*!< Reverse body biasing for Soc
100 kResc_RBB_LPSR = 40U, /*!< Reverse body biasing for LPSR power domain. */
114 …urce constraints definition of CPU platform (suitable for CM7 and CM4 processors), with support fo…
130 * @brief Resource constraints definition of OSC_RC_16M, with support for 2 modes:
138 * @brief Resource constraints definition of OSC_RC_48M, with support for 2 modes:
146 * @brief Resource constraints definition of OSC_RC_48M_DIV2, with support for 2 modes:
154 * @brief Resource constraints definition of OSC_RC_400M, with support for 2 modes:
162 * @brief Resource constraints definition of OSC_RC_24M, with support for 2 modes:
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1175/ |
| D | fsl_pm_device.h | 53 kResc_CPU_PLATFORM = 0U, /*!< CPU platform, this resource is suitable for CM7 and CM4. */
97 kResc_FBB_M7 = 38U, /*!< Forward body biasing for CM7 platform. */
98 kResc_RBB_SOC = 39U, /*!< Reverse body biasing for Soc
100 kResc_RBB_LPSR = 40U, /*!< Reverse body biasing for LPSR power domain. */
114 …urce constraints definition of CPU platform (suitable for CM7 and CM4 processors), with support fo…
130 * @brief Resource constraints definition of OSC_RC_16M, with support for 2 modes:
138 * @brief Resource constraints definition of OSC_RC_48M, with support for 2 modes:
146 * @brief Resource constraints definition of OSC_RC_48M_DIV2, with support for 2 modes:
154 * @brief Resource constraints definition of OSC_RC_400M, with support for 2 modes:
162 * @brief Resource constraints definition of OSC_RC_24M, with support for 2 modes:
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/common/ |
| D | fsl_common.h | 45 /*! @brief Construct the version number for drivers.
47 * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M)
83 kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
84 kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
85 kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
86 kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
87 kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
88 kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
89 kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
90 kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
[all …]
|
| /hal_nxp-latest/s32/soc/s32k344/include/ |
| D | Emios_Icu_Ip_SA_Init_PBcfg.h | 106 /** @brief Macros for indicate EMIOS interrupts used by ICU. */
111 /** @brief Macros for indicate EMIOS interrupts used. */
119 /** @brief Macros for indicate EMIOS interrupts used by ICU. */
124 /** @brief Macros for indicate EMIOS interrupts used. */
132 /** @brief Macros for indicate EMIOS interrupts used by ICU. */
137 /** @brief Macros for indicate EMIOS interrupts used. */
145 /** @brief Macros for indicate EMIOS interrupts used by ICU. */
150 /** @brief Macros for indicate EMIOS interrupts used. */
158 /** @brief Macros for indicate EMIOS interrupts used by ICU. */
163 /** @brief Macros for indicate EMIOS interrupts used. */
[all …]
|
| /hal_nxp-latest/mcux/middleware/wifi_nxp/wifidriver/incl/ |
| D | mlan_ioctl.h | 19 /** Enumeration for IOCTL request ID */
259 /** Enumeration for the action of IOCTL request */
270 /** Enumeration for generic enable/disable */
277 /** Enumeration for scan mode */
286 /** Enumeration for scan type */
302 /** BSS index number for multiple BSS support */
317 /** Reserved for MOAL module */
327 /** Max passive scan time for each channel in milliseconds */
330 /** Max active scan time for each channel in milliseconds */
345 * @brief Sub-structure passed in wlan_ioctl_get_scan_table_entry for each BSS
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/drivers/caam/ |
| D | fsl_caam.h | 53 * - Add data offset feature to provide support for mirrored (high-speed) memory.
59 * - Support EXTENDED data size for all AES, HASH and RNG operations.
64 * - Added API for Blob functions and CRC
74 * - Add support for SHA HMAC.
110 void *userData; /*!< Parameter for CAAM job complete callback */
121 /*! @brief Memory buffer to hold CAAM descriptor for AESA ECB job */
124 /*! @brief Memory buffer to hold CAAM descriptor for AESA CBC job */
127 /*! @brief Memory buffer to hold CAAM descriptor for AESA CTR job */
130 /*! @brief Memory buffer to hold CAAM descriptor for AESA CCM job */
133 /*! @brief Memory buffer to hold CAAM descriptor for AESA GCM job */
[all …]
|
| /hal_nxp-latest/s32/drivers/s32ze/Mcu/src/ |
| D | Clock_Ip_Frequency.c | 478 &Clock_Ip_Get_FIRC_CLK_Frequency, /* clock name for 0 hardware value */
479 &Clock_Ip_Get_Zero_Frequency, /* clock name for 1 hardware value */
480 &Clock_Ip_Get_FXOSC_CLK_Frequency, /* clock name for 2 hardware value */
481 &Clock_Ip_Get_Zero_Frequency, /* clock name for 3 hardware value */
482 &Clock_Ip_Get_Zero_Frequency, /* clock name for 4 hardware value */
483 &Clock_Ip_Get_Zero_Frequency, /* clock name for 5 hardware value */
484 &Clock_Ip_Get_Zero_Frequency, /* clock name for 6 hardware value */
485 &Clock_Ip_Get_Zero_Frequency, /* clock name for 7 hardware value */
486 &Clock_Ip_Get_Zero_Frequency, /* clock name for 8 hardware value */
487 &Clock_Ip_Get_Zero_Frequency, /* clock name for 9 hardware value */
[all …]
|
| /hal_nxp-latest/s32/soc/s32z270/include/ |
| D | Emios_Icu_Ip_Cfg.h | 96 /** @brief Macros for indicate EMIOS interrupts used by ICU. */
101 /** @brief Macros for indicate EMIOS interrupts used. */
109 /** @brief Macros for indicate EMIOS interrupts used by ICU. */
114 /** @brief Macros for indicate EMIOS interrupts used. */
122 /** @brief Macros for indicate EMIOS interrupts used by ICU. */
127 /** @brief Macros for indicate EMIOS interrupts used. */
135 /** @brief Macros for indicate EMIOS interrupts used by ICU. */
140 /** @brief Macros for indicate EMIOS interrupts used. */
148 /** @brief Macros for indicate EMIOS interrupts used by ICU. */
153 /** @brief Macros for indicate EMIOS interrupts used. */
[all …]
|
| /hal_nxp-latest/mcux/middleware/mcux-sdk-middleware-usb/output/source/device/class/ |
| D | usb_device_ccid.h | 194 uint8_t bSlot; /*!< Identifies the slot number for this command */
195 uint8_t bSeq; /*!< Sequence number for command */
215 uint8_t bSlot; /*!< Identifies the slot number for this command */
216 uint8_t bSeq; /*!< Sequence number for command */
218 uint8_t bRFU[2]; /*!< Reserved for Future Use */
232 uint8_t bSlot; /*!< Identifies the slot number for this command */
233 uint8_t bSeq; /*!< Sequence number for command */
234 uint8_t bRFU[3]; /*!< Reserved for Future Use */
248 uint8_t bSlot; /*!< Identifies the slot number for this command */
249 uint8_t bSeq; /*!< Sequence number for command */
[all …]
|
| /hal_nxp-latest/s32/drivers/s32ze/Mcl/include/ |
| D | Emios_Mcl_Ip_Irq.h | 513 * @brief Interrupt handler for EMIOS channel 0 for Emios instance 0
529 * @brief Interrupt handler for EMIOS channel 1 for Emios instance 0
545 * @brief Interrupt handler for EMIOS channel 2 for Emios instance 0
561 * @brief Interrupt handler for EMIOS channel 3 for Emios instance 0
577 * @brief Interrupt handler for EMIOS channel 4 for Emios instance 0
593 * @brief Interrupt handler for EMIOS channel 5 for Emios instance 0
609 * @brief Interrupt handler for EMIOS channel 6 for Emios instance 0
625 * @brief Interrupt handler for EMIOS channel 7 for Emios instance 0
641 * @brief Interrupt handler for EMIOS channel 8 for Emios instance 0
657 * @brief Interrupt handler for EMIOS channel 9 for Emios instance 0
[all …]
|
| /hal_nxp-latest/mcux/middleware/wifi_nxp/incl/port/mbedtls/ |
| D | wpa_supp_els_pkc_mbedtls_config.h | 23 * See the License for the specific language governing permissions and
62 * The compiler has support for asm().
64 * Requires support for asm() in compiler.
82 * The platform lacks support for double-width integer division (64-bit
94 * and can be linked with an implementation of division for that type.
98 * Note that division for the native integer type is always required.
101 * cases it is also desirable to disable some double-width operations. For
110 * The platform lacks support for 32x32 -> 64-bit multiplication.
156 * System has time.h, time(), and an implementation for
166 * the documentation for mbedtls_platform_gmtime_r() for more information.
[all …]
|
| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_COMMON.h | 12 * @brief Peripheral Access Layer for S32Z2
14 * This file contains register definitions and macros for easy access to their
25 * The SoC header defines typedef for all modules.
29 * The SoC header defines macros for all modules and registers.
33 * These are generated macros used for accessing the bit-fields from registers.
37 * The supported compilers use more than 31 significant characters for identifiers.
41 * The supported compilers use more than 31 significant characters for identifiers.
45 * The supported compilers use more than 31 significant characters for identifiers.
49 * The supported compilers use more than 31 significant characters for identifiers.
88 * \li for automatic generation of peripheral register debug information.
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/components/log/ |
| D | fsl_component_log_config.h | 21 * @details The feature is used to configure the log feature for the specific module.
44 * For example,
63 * @details The feature is used to configure the log color feature for all of log component.@n
66 …* For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->D…
67 * For KEIL, click "Options for Target...", define it in "C/C++->Preprocessor Symbols->Define".@n
68 * For ARMGCC, open CmakeLists.txt and add the following lines,@n
69 * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DLOG_ENABLE_COLOR=0")" for debug target.@n
70 …* "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DLOG_ENABLE_COLOR=0")" for release target.…
71 …* For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings…
78 /*! @brief Whether enable timestamp global feature for log, 1 - enable, 0 - disable.
[all …]
|
| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/include/ |
| D | Compiler.h | 12 * @details The file Compiler.h provides macros for the encapsulation of definitions and
68 * @brief The memory class AUTOMATIC shall be provided as empty definition, used for the declaration
76 * necessary for defining pointer types, with e.g. P2VAR, where the macros require two
91 /* Prototypes for intrinsic functions */
93 * @brief The compiler abstraction shall provide the INLINE define for abstraction of the keyword
99 * @brief The compiler abstraction shall provide the LOCAL_INLINE define for abstraction of the
105 * @brief Compiler abstraction for specifying an interrupt handler.
110 * @brief Compiler abstraction for the asm keyword.
115 * @brief Compiler abstraction for the asm keyword.
120 * @brief Compiler abstraction for the data alignment
[all …]
|
| /hal_nxp-latest/s32/drivers/s32k3/BaseNXP/include/ |
| D | Compiler.h | 12 * @details The file Compiler.h provides macros for the encapsulation of definitions and
68 * @brief The memory class AUTOMATIC shall be provided as empty definition, used for the declaration
76 * necessary for defining pointer types, with e.g. P2VAR, where the macros require two
91 /* Prototypes for intrinsic functions */
93 * @brief The compiler abstraction shall provide the INLINE define for abstraction of the keyword
99 * @brief The compiler abstraction shall provide the LOCAL_INLINE define for abstraction of the
105 * @brief Compiler abstraction for specifying an interrupt handler.
110 * @brief Compiler abstraction for the asm keyword.
115 * @brief Compiler abstraction for the asm keyword.
120 * @brief Compiler abstraction for the data alignment
[all …]
|
| /hal_nxp-latest/s32/drivers/s32k1/BaseNXP/include/ |
| D | Compiler.h | 12 * @details The file Compiler.h provides macros for the encapsulation of definitions and
68 * @brief The memory class AUTOMATIC shall be provided as empty definition, used for the declaration
76 * necessary for defining pointer types, with e.g. P2VAR, where the macros require two
91 /* Prototypes for intrinsic functions */
93 * @brief The compiler abstraction shall provide the INLINE define for abstraction of the keyword
99 * @brief The compiler abstraction shall provide the LOCAL_INLINE define for abstraction of the
105 * @brief Compiler abstraction for specifying an interrupt handler.
110 * @brief Compiler abstraction for the asm keyword.
115 * @brief Compiler abstraction for the asm keyword.
120 * @brief Compiler abstraction for the data alignment
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/scripts/kconfig/ |
| D | kconfiglib.py | 8 Kconfiglib is a Python 2/3 library for scripting and extracting information
12 See the homepage at https://github.com/ulfalizer/Kconfiglib for a longer
23 For the Linux kernel, a handy interface is provided by the
36 Look further down for a motivation for the Makefile patch and for instructions
75 To get a feel for the API, try evaluating and printing the symbols in
96 See the examples/ subdirectory for example scripts.
142 Search the top-level Makefile for "Additional ARCH settings" to see other
143 possibilities for ARCH and SRCARCH.
156 For symbols with prompts, the visibility of the symbol is determined by the
193 In this example, A && B && C && D (the prompt condition) needs to be non-n for
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9131/ |
| D | MIMX9131.h | 7 ** IAR ANSI C/C++ Compiler for ARM
15 ** CMSIS Peripheral Access Layer for MIMX9131
35 * @brief CMSIS Peripheral Access Layer for MIMX9131
37 * CMSIS Peripheral Access Layer for MIMX9131
415 * @brief Structure for the DMA3 hardware request
417 * Defines the structure for the DMA hardware request collections. The user can configure the
466 * @brief Structure for the DMA4 hardware request
468 * Defines the structure for the DMA hardware request collections. The user can configure the
749 /*! TSAMP - Sample Time for Calibration
935 * 0b0..ADC is ready for use
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/K32L2B21A/ |
| D | K32L2B21A.h | 8 ** Compilers: Freescale C/C++ for Embedded ARM
10 ** IAR ANSI C/C++ Compiler for ARM
19 ** CMSIS Peripheral Access Layer for K32L2B21A
41 * @brief CMSIS Peripheral Access Layer for K32L2B21A
43 * CMSIS Peripheral Access Layer for K32L2B21A
90 SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
91 SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */
97 TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
98 TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
99 TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/K32L2B31A/ |
| D | K32L2B31A.h | 8 ** Compilers: Freescale C/C++ for Embedded ARM
10 ** IAR ANSI C/C++ Compiler for ARM
19 ** CMSIS Peripheral Access Layer for K32L2B31A
41 * @brief CMSIS Peripheral Access Layer for K32L2B31A
43 * CMSIS Peripheral Access Layer for K32L2B31A
90 SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
91 SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */
97 TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
98 TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
99 TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/K32L2B11A/ |
| D | K32L2B11A.h | 8 ** Compilers: Freescale C/C++ for Embedded ARM
10 ** IAR ANSI C/C++ Compiler for ARM
19 ** CMSIS Peripheral Access Layer for K32L2B11A
41 * @brief CMSIS Peripheral Access Layer for K32L2B11A
43 * CMSIS Peripheral Access Layer for K32L2B11A
90 SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
91 SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */
97 TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
98 TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
99 TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
[all …]
|
