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/Zephyr-Core-3.5.0/dts/bindings/pinctrl/
Dnxp,s32k3-pinctrl.yaml58 - slew rate "fastest"
98 - "fastest"
100 default: "fastest"
102 Slew rate control. Can be either slowest or fastest setting.
/Zephyr-Core-3.5.0/tests/lib/devicetree/api_ext/
Dtestcase.yaml5 # will mostly likely be the fastest.
/Zephyr-Core-3.5.0/tests/lib/devicetree/api/
Dtestcase.yaml5 # will mostly likely be the fastest.
/Zephyr-Core-3.5.0/tests/lib/devicetree/devices/
Dtestcase.yaml5 # will mostly likely be the fastest.
/Zephyr-Core-3.5.0/subsys/logging/
DKconfig.mode46 fastest way of getting logs out. The logs are redirected at the function
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec1501/
Ddevice_power.c37 * Light sleep: PLL remains on. Fastest wake latency.
/Zephyr-Core-3.5.0/include/zephyr/logging/
Dlog_msg.h140 * directly to the message space. It is the fastest method but requires
372 * content is written directly to the message. It is the fastest but cannot
/Zephyr-Core-3.5.0/subsys/sd/
Dmmc.c92 /* Sets card to the fastest timing mode (using CMD6) and SDHC to max frequency */
190 /* Set timing to fastest supported */ in mmc_card_init()
/Zephyr-Core-3.5.0/soc/arm/nxp_lpc/lpc55xxx/
Dsoc.c120 /* Set Voltage for one of the fastest clock outputs: System clock output */ in clock_init()
/Zephyr-Core-3.5.0/soc/nios2/nios2f-zephyr/cpu/
Dghrd_10m50da.qsys346 … 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MO…
533 … 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MO…
662 … 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MO…
831 … 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MO…
Dghrd_10m50da.sopcinfo230 … 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MO…
3370 … 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MO…
10439 … 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MO…
13823 … 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MO…
/Zephyr-Core-3.5.0/doc/kernel/services/timing/
Dclocks.rst24 represents the fastest cycle counter that the operating system is able
/Zephyr-Core-3.5.0/boards/arm/v2m_musca_b1/doc/
Dindex.rst259 it offers the fastest boot method.
/Zephyr-Core-3.5.0/boards/arm/v2m_musca_s1/doc/
Dindex.rst253 it offers the fastest boot method. Musca-S1 test chip also support to boot from
/Zephyr-Core-3.5.0/doc/develop/application/
Dindex.rst861 Application development is usually fastest when changes are continually tested.
/Zephyr-Core-3.5.0/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/
Dradio.c1815 /* NOTE: use fastest data rate as tx data needs to be prepared before in radio_ccm_ext_tx_pkt_set()
/Zephyr-Core-3.5.0/tests/net/conn_mgr_conn/src/
Dmain.c160 * This is not guaranteed to execute in the fastest possible time, nor is it technically guaranteed