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/Zephyr-latest/samples/drivers/w1/scanner/
DREADME.rst1 .. zephyr:code-sample:: w1-scanner
2 :name: 1-Wire scanner
3 :relevant-api: w1_interface
5 Scan for 1-Wire devices and print their family ID and serial number.
10 This sample demonstrates how to scan for 1-Wire devices. It runs the 1-Wire
11 scan routine once and prints the family id as well as serial number of the
20 .. zephyr-app-commands::
21 :zephyr-app: samples/drivers/w1/scanner
23 :gen-args: -DDTC_OVERLAY_FILE=w1_serial.overlay
30 .. code-block:: console
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/Zephyr-latest/tests/drivers/build_all/sensor/
Dw1.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 family-code = <0x28>;
18 family-code = <0x10>;
/Zephyr-latest/tests/drivers/w1/w1_api/
Dw1_devices.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 slave_1: dummy-slave-1 {
9 compatible = "vnd,w1-device";
10 family-code = <0x28>;
11 overdrive-speed;
15 slave_2: dummy-slave-2 {
16 compatible = "vnd,w1-device";
17 family-code = <0x29>;
/Zephyr-latest/dts/bindings/w1/
Dw1-slave.yaml2 # SPDX-License-Identifier: Apache-2.0
8 on-bus: w1
11 family-code:
14 8-bit 1-Wire family code, which is also part of the 64 bit ROM ID.
15 overdrive-speed:
/Zephyr-latest/doc/hardware/porting/
Dsoc_porting.rst18 - SoC: the exact system on a chip the board's CPU is part of.
19 - SoC series: a group of tightly related SoCs.
20 - SoC family: a wider group of SoCs with similar characteristics.
21 - CPU Cluster: a cluster of one or more CPU cores.
22 - CPU core: a particular CPU instance of a given architecture.
23 - Architecture: an instruction set architecture.
39 in Zephyr, for example ``./scripts/list_hardware.py --soc-root=. --socs`` from
48 structure under ``<your-repo>/soc`` is permitted.
50 :zephyr_file:`dts/bindings/vendor-prefixes.txt`. If the SoC vendor does not
57 organized in sub-folders in a common SoC Family or SoC Series tree.
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/Zephyr-latest/samples/drivers/spi_flash_at45/
DREADME.rst1 .. zephyr:code-sample:: spi-flash-at45
3 :relevant-api: flash_interface
5 Use the AT45 family DataFlash driver to interact with the flash memory over SPI.
10 This sample shows how to use the AT45 family DataFlash driver and how to
14 increasing (and overflowing at the 8-bit range) values and then reads it back
19 The :zephyr_file:`samples/drivers/spi_flash_at45/overlay-pm.conf` enables the
21 The :zephyr_file:`samples/drivers/spi_flash_at45/overlay-page_layout.conf`
25 the Read-Modify-Write functionality of DataFlash chips and does not perform
35 AT45 family chips by just providing a corresponding overlay file.
40 The code can be found in :zephyr_file:`samples/drivers/spi_flash_at45`.
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/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace15_mtpm/
Dadsp_ipc_regs.h2 * SPDX-License-Identifier: Apache-2.0
13 * Inter Processor Communication - used for sending interrupts to and receiving
20 * @brief IPC registers layout for Intel ADSP ACE1X SoC family.
45 * On ACE SoC family boards TDA bit 31 (BUSY) during IPC doorbell acknowledgment
46 * must be cleared (!), not set (in contrary to CAVS SoC family boards).
54 * @brief ACE SoC family Intra DSP Communication.
56 * ACE SoC platform family provides an array of IPC endpoints to be used for
57 * peer-to-peer communication between DSP cores - master to slave and backwards.
59 * @code
67 * Each connection is organized into two "agents" ("A" - master core and "B" - slave core).
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/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace20_lnl/
Dadsp_ipc_regs.h2 * SPDX-License-Identifier: Apache-2.0
13 * Inter Processor Communication - used for sending interrupts to and receiving
20 * @brief IPC registers layout for Intel ADSP ACE2X SoC family.
45 * On ACE SoC family boards TDA bit 31 (BUSY) during IPC doorbell acknowledgment
46 * must be cleared (!), not set (in contrary to CAVS SoC family boards).
54 * @brief ACE SoC family Intra DSP Communication.
56 * ACE SoC platform family provides an array of IPC endpoints to be used for
57 * peer-to-peer communication between DSP cores - master to slave and backwards.
59 * @code
67 * Each connection is organized into two "agents" ("A" - master core and "B" - slave core).
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/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace30/
Dadsp_ipc_regs.h2 * SPDX-License-Identifier: Apache-2.0
13 * Inter Processor Communication - used for sending interrupts to and receiving
20 * @brief IPC registers layout for Intel ADSP ACE1X SoC family.
42 * On ACE SoC family boards TDA bit 31 (BUSY) during IPC doorbell acknowledgment
43 * must be cleared (!), not set (in contrary to CAVS SoC family boards).
53 * @brief ACE SoC family Intra DSP Communication.
55 * ACE SoC platform family provides an array of IPC endpoints to be used for
56 * peer-to-peer communication between DSP cores - master to slave and backwards.
58 * @code
66 * Each connection is organized into two "agents" ("A" - master core and "B" - slave core).
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/Zephyr-latest/doc/connectivity/networking/api/
Dnet_pkt.rst37 All net_pkt objects come from a pre-defined pool of struct net_pkt.
40 .. code-block:: c
49 .. code-block:: c
59 .. code-block:: c
66 .. code-block:: c
68 pkt = net_pkt_alloc_with_buffer(iface, size, family, proto, timeout);
84 interface set. This works if the family of the packet is unknown at
87 .. code-block:: c
97 The network interface, the family, and the protocol of the packet are
100 know the MTU and then the family and protocol for the headers space
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Dsockets.rst22 * Is namespaced by default, to avoid name conflicts with well-known
31 ``listen()``, ``accept()``, ``fcntl()`` (to set non-blocking mode),
45 API aggressively employs the short-read/short-write property of the POSIX API
60 See :zephyr:code-sample:`sockets-echo-server` and :zephyr:code-sample:`sockets-echo-client`
95 - ``TLS_CREDENTIAL_CA_CERTIFICATE``
96 - ``TLS_CREDENTIAL_SERVER_CERTIFICATE``
97 - ``TLS_CREDENTIAL_PRIVATE_KEY``
98 - ``TLS_CREDENTIAL_PSK``
99 - ``TLS_CREDENTIAL_PSK_ID``
104 .. code-block:: c
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/Zephyr-latest/tests/net/socket/register/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
19 int family; member
31 .test_case.family = AF_INET,
38 .test_case.family = AF_INET6,
46 .test_case.family = AF_UNSPEC,
49 .result = -1,
54 .test_case.family = AF_INET,
61 .test_case.family = AF_INET6,
68 .test_case.family = AF_INET,
75 .test_case.family = AF_INET6,
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/Zephyr-latest/samples/drivers/ipm/ipm_mcux/
DREADME.rst1 .. zephyr:code-sample:: ipm-mcux
3 :relevant-api: ipm_interface
5 Implement inter-processor mailbox (IPM) on NXP LPC family.
10 Some NXP microcontrollers from LPC family are dual-core, this
15 - :zephyr:board:`lpcxpresso54114`, two core processors (Cortex-M4F and Cortex-M0+)
16 - :zephyr:board:`lpcxpresso55s69`, two core processors (dual Cortex-M33)
21 - :zephyr:board:`lpcxpresso54114` board
22 - :zephyr:board:`lpcxpresso55s69` board
27 .. zephyr-app-commands::
28 :zephyr-app: samples/drivers/ipm/ipm_mcux
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/Zephyr-latest/samples/sensor/ds18b20/boards/
Dserial_overlay.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 w1_0: w1-zephyr-serial-0 {
11 compatible = "zephyr,w1-serial";
12 #address-cells = <1>;
13 #size-cells = <0>;
18 family-code = <0x28>;
/Zephyr-latest/arch/nios2/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
23 menu "Nios II Family Options"
49 and then jumps to __start. This code is typically located at the very
51 nios2-download tool since it refuses to load data anywhere other than
58 human-readable form, at the expense of code size. For example,
59 the cause code for an exception will be supplemented by a string
60 describing what that cause code means.
75 same C file as the code that uses it.
/Zephyr-latest/include/zephyr/drivers/
Dw1.h5 * SPDX-License-Identifier: Apache-2.0
10 * @brief Public 1-Wire Driver APIs
27 * @brief 1-Wire Interface
28 * @defgroup w1_interface 1-Wire Interface
46 (FOR_EACH(F1, (+), DT_SUPPORTS_DEP_ORDS(node_id)) - 1)
53 * @brief Defines the 1-Wire master settings types, which are runtime configurable.
74 /** Configuration common to all 1-Wire master implementations. */
80 /** Data common to all 1-Wire master implementations. */
118 struct w1_master_data *ctrl_data = (struct w1_master_data *)dev->data; in z_impl_w1_change_bus_lock()
119 const struct w1_driver_api *api = (const struct w1_driver_api *)dev->api; in z_impl_w1_change_bus_lock()
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/Zephyr-latest/samples/sensor/ds18b20/
Darduino_serial.overlay4 * SPDX-License-Identifier: Apache-2.0
9 * Requires external circuit to provide an open-drain interface.
15 w1_0: w1-zephyr-serial-0 {
16 compatible = "zephyr,w1-serial";
17 #address-cells = <1>;
18 #size-cells = <0>;
23 family-code = <0x28>;
/Zephyr-latest/arch/arm/core/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
29 This option signifies the use of a CPU of the Cortex-M family.
44 This option signifies the use of a CPU of the Cortex-R family.
66 This option signifies the use of a CPU of the Cortex-A family.
69 # GDB for ARM expects up to 18 4-byte plus 8 12-byte
70 # registers - 336 HEX letters
76 From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
78 Thumb-2 technology is the instruction set underlying the ARM Cortex
80 efficiency, and code density for a wide range of embedded
83 Thumb-2 technology builds on the success of Thumb, the innovative
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/Zephyr-latest/boards/atmel/sam0/samc21n_xpro/doc/
Dindex.rst7 prototyping with the SAM C21N Cortex®-M0+ processor-based
15 - SAMC21N18A ARM Cortex-M0+ processor at 48 MHz
16 - 32.768 kHz crystal oscillator
17 - 256 KiB flash memory, 32 KiB of RAM, 8KB RRW flash
18 - One yellow user LED
19 - One mechanical user push button
20 - One reset button
21 - One QTouch® button
22 - On-board USB based EDBG unit with serial console
23 - Two CAN transceivers
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/Zephyr-latest/boards/atmel/sam0/samd21_xpro/doc/
Dindex.rst7 prototyping with the SAM D21 Cortex®-M0+ processor-based
15 - SAMD21J18 ARM Cortex-M0+ processor at 48 MHz
16 - 32.768 kHz crystal oscillator
17 - 256 KiB flash memory and 32 KiB of RAM
18 - One yellow user LED
19 - One mechanical user push button
20 - One reset button
21 - On-board USB based EDBG unit with serial console
29 .. list-table::
30 :header-rows: 1
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/Zephyr-latest/doc/_extensions/zephyr/domain/templates/
Dboard-catalog.html3 SPDX-License-Identifier: Apache-2.0
6 <form class="filter-form" aria-label="Filter boards by name, architecture, and vendor">
8 <div class="form-group" style="flex-basis: 100%">
15 <div class="form-group">
17 <div class="select-container">
25 <option value="riscv">RISC-V</option>
34 <div class="form-group" style="flex-basis: 400px">
36 <div class="select-container">
40 …per vendor name is not feasible in Jinja, the option list is sorted in the JavaScript code later #}
41 {% for vendor in (boards | items | map(attribute='1.vendor') | unique ) -%}
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/Zephyr-latest/doc/security/media/
Dsensor-model.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
2 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
5 …-face font-family="Helvetica" font-size="16" units-per-em="1000" underline-position="-75.68359" un…
6 <font-face-src>
7 <font-face-name name="Helvetica"/>
8 </font-face-src>
9 </font-face>
10 …nits="strokeWidth" id="FilledArrow_Marker" stroke-linejoin="miter" stroke-miterlimit="10" viewBox=…
12 <path d="M 8 0 L 0 -3 L 0 3 Z" fill="currentColor" stroke="currentColor" stroke-width="1"/>
15 …ts="strokeWidth" id="FilledArrow_Marker_2" stroke-linejoin="miter" stroke-miterlimit="10" viewBox=…
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/Zephyr-latest/boards/atmel/sam0/samr34_xpro/doc/
Dindex.rst7 prototyping with the SAM R34 Cortex®-M0+ processor-based
12 The SAMR34 and SAMR35 parts are produced as a System-in-Package (SiP),
20 - SAMR34J18 ARM Cortex-M0+ processor at 48 MHz
21 - 32.768 kHz crystal oscillator
22 - 256 KiB flash memory, 32 KiB of SRAM, 8KB Low Power SRAM
23 - One yellow user LED
24 - One mechanical user push button
25 - One reset button
26 - On-board USB based EDBG unit with serial console
34 .. list-table::
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/Zephyr-latest/scripts/west_commands/runners/
Dnrfutil.py3 # SPDX-License-Identifier: Apache-2.0
18 '''Runner front-end for nrfutil.'''
20 def __init__(self, cfg, family, softreset, dev_id, erase=False, argument
24 super().__init__(cfg, family, softreset, dev_id, erase, reset,
37 def tool_opt_help(cls) -> str:
38 return 'Additional options for nrfutil, e.g. "--log-level"'
52 parser.add_argument('--suit-manifest-starter', required=False,
59 cmd = ['nrfutil', '--json', 'device'] + args
67 # https://github.com/ndjson/ndjson-spec
71 if 'x-execute-batch' in args:
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/Zephyr-latest/doc/hardware/peripherals/
Dw1.rst3 1-Wire Bus
9 1-Wire is a low speed half-duplex serial bus using only a single wire plus
11 Similarly to I2C, 1-Wire uses a bidirectional open-collector data line,
14 The 1-Wire bus supports longer bus lines than I2C, while it reaches speeds of up
23 .. figure:: 1-Wire_bus_topology.drawio.svg
25 :alt: 1-Wire bus topology
27 A typical 1-Wire bus topology
30 .. _w1-master-api:
35 Zephyr's 1-Wire Master API is used to interact with 1-Wire slave devices like
42 It is the only hardware-dependent layer in Zephyr.
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