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/Zephyr-Core-3.5.0/dts/bindings/espi/
Dnuvoton,npcx-espi.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Nuvoton, NPCX-eSPI node
6 compatible: "nuvoton,npcx-espi"
8 include: [espi-controller.yaml, pinctrl-device.yaml]
19 pinctrl-0:
22 pinctrl-names:
25 espi-rst-wui:
29 Mapping table between Wake-Up Input (WUI) and ESPI_RST signal.
31 For example the WUI mapping on NPCX7 would be
32 espi-rst-wui = <&wui_cr_sin1>;
/Zephyr-Core-3.5.0/dts/arm/nuvoton/npcx/
Dnpcx-espi-vws-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/espi/npcx_espi.h>
10 * Nuvoton NPCX eSPI Virtual Wires Mapping Table
11 * |--------------------------------------------------------------------------|
13 * |--------------------------------------------------------------------------|
14 * | Input (Master-to-Slave) Virtual Wires |
15 * |--------------------------------------------------------------------------|
21 * |--------------------------------------------------------------------------|
22 * | Output (Slave-to-Master) Virtual Wires |
23 * |--------------------------------------------------------------------------|
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Dnpcx.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/adc/adc.h>
11 #include <zephyr/dt-bindings/clock/npcx_clock.h>
12 #include <zephyr/dt-bindings/flash_controller/npcx_fiu_qspi.h>
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #include <zephyr/dt-bindings/pinctrl/npcx-pinctrl.h>
16 #include <zephyr/dt-bindings/pwm/pwm.h>
17 #include <zephyr/dt-bindings/sensor/npcx_tach.h>
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/Zephyr-Core-3.5.0/drivers/espi/
Despi_npcx.c4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/espi.h>
14 #include <zephyr/dt-bindings/espi/npcx_espi.h>
25 LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
31 /* mapping table between eSPI reset signal and wake-up input */
52 ((struct espi_reg *)((const struct espi_npcx_config *)(dev)->config)->base)
54 /* eSPI channels */
62 /* eSPI max supported frequency */
80 /* eSPI cycle type field for OOB and FLASH channels */
92 /* eSPI bus interrupt configuration structure and macro function */
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