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/Zephyr-Core-3.6.0/samples/drivers/clock_control_litex/
DREADME.rst11 …lock Manager (MMCM) module to generate up to 7 clocks with defined phase, frequency and duty cycle.
35 …k1`` with default frequency set to 100MHz, 0 degrees phase offset and 50% duty cycle. Special care…
48 | This code will try to set on ``clk0`` frequency 50MHz, 90 degrees of phase offset and 75% duty cy…
57 .duty = 75,
67 Clock output status (frequency, duty and phase offset) can be acquired with function ``clock_contro…
77 * Duty cycle range,
79 * Setting frequency, duty and phase at once, then check clock status and rate,
106 [00:00:00.280,000] <inf> CLK_CTRL_LITEX: CLKOUT0: set duty: 50%
109 [00:00:00.400,000] <inf> CLK_CTRL_LITEX: CLKOUT1: set duty: 50%
120 [00:00:00.590,000] <inf> CLK_CTRL_LITEX: CLKOUT0: set duty: 25%
[all …]
/Zephyr-Core-3.6.0/dts/bindings/clock/
Dlitex,clkout.yaml40 litex,clock-duty-num:
44 default duty cycle numerator value
46 litex,clock-duty-den:
50 default duty cycle denominator value
Dmicrochip,xec-pcr.yaml51 clk32kmon-duty-cycle-var-max:
55 Maximum duty cycle variation. Difference in units of 48HMz between
/Zephyr-Core-3.6.0/samples/drivers/clock_control_litex/src/
Dmain.c25 /* Values for duty test */
75 printf("CLKOUT%d: get_status: rate:%d phase:%d duty:%d\n", in litex_clk_test_getters()
76 i, setup.rate, setup.phase, setup.duty); in litex_clk_test_getters()
89 .duty = LITEX_TEST_SINGLE_DUTY_VAL, in litex_clk_test_single()
95 .duty = LITEX_TEST_SINGLE_DUTY_VAL2, in litex_clk_test_single()
121 .duty = LITEX_TEST_FREQUENCY_DUTY_VAL, in litex_clk_test_freq()
184 .duty = LITEX_TEST_PHASE_DUTY_VAL, in litex_clk_test_phase()
190 .duty = LITEX_TEST_PHASE_DUTY_VAL in litex_clk_test_phase()
226 .duty = 0 in litex_clk_test_duty()
232 .duty = 0 in litex_clk_test_duty()
[all …]
/Zephyr-Core-3.6.0/drivers/clock_control/
Dclock_control_litex.c441 lcko->def.freq, lcko->def.duty.num, in litex_clk_print_params()
442 lcko->def.duty.den, lcko->def.phase); in litex_clk_print_params()
444 LOG_DBG("div: %u freq: %u duty: %u/%u phase: %d per_off: %u", in litex_clk_print_params()
446 lcko->ts_config.duty.num, lcko->ts_config.duty.den, in litex_clk_print_params()
449 LOG_DBG("div: %u freq: %u duty: %u/%u phase: %d per_off: %u", in litex_clk_print_params()
451 lcko->config.duty.num, lcko->config.duty.den, in litex_clk_print_params()
839 * Duty Cycle
842 /* Returns accurate duty ratio of given clkout*/
844 struct clk_duty *duty) in litex_clk_get_duty_cycle() argument
864 /* get duty 50% when divider is off or fractional is enabled */ in litex_clk_get_duty_cycle()
[all …]
Dclock_control_litex.h63 "Invalid default duty"); \
71 lcko->def.duty.num = CLKOUT_DUTY_NUM(N); \
72 lcko->def.duty.den = CLKOUT_DUTY_DEN(N); \
171 struct clk_duty duty; member
207 struct clk_duty duty; member
DKconfig.litex13 such as phase, duty cycle, frequency for up to 7
/Zephyr-Core-3.6.0/include/zephyr/drivers/clock_control/
Dclock_control_litex.h34 * @param duty Duty cycle of clock signal in percent
41 uint8_t duty; member
/Zephyr-Core-3.6.0/drivers/pwm/
Dpwm_intel_blinky.c44 uint32_t duty; in bk_intel_set_cycles() local
57 duty = (pulse_cycles * PWM_DUTY_MAX) / period_cycles; in bk_intel_set_cycles()
59 if (duty) { in bk_intel_set_cycles()
60 val = PWM_DUTY_MAX - duty; in bk_intel_set_cycles()
73 if (duty > PWM_DUTY_MAX) { in bk_intel_set_cycles()
DKconfig.it8xxx213 eight PWM channels each with 8-bit duty cycle.
Dpwm_mchp_xec_bbled.c42 /* BBLED PWM mode uses the duty cycle to set the PWM frequency:
51 * Duty cycle is derived from LIMITS register MINIMUM 8-bit field
58 * BBLED PWM mode duty cycle specified by 8-bit MIN field of the LIMITS register
160 /* BBLED-PWM duty cycle set in 8-bit MINIMUM field of BBLED LIMITS register.
163 * 1 <= Limits.Minimum <= 254 duty cycle
183 * LIMITS.MIN = duty cycle = [1, 254]
282 /* PWM mode: Limits minimum duty cycle == 0 -> LED output is fully OFF */ in pwm_bbled_xec_set_cycles()
285 /* PWM mode: Limits minimum duty cycle == full value -> LED output is fully ON */ in pwm_bbled_xec_set_cycles()
Dpwm_mc_esp32.c70 uint32_t duty; member
101 duty_type = channel->duty == 0 ? in mcpwm_esp32_duty_set()
102 MCPWM_HAL_GENERATOR_MODE_FORCE_HIGH : channel->duty == 100 ? in mcpwm_esp32_duty_set()
105 duty_type = channel->duty == 0 ? in mcpwm_esp32_duty_set()
106 MCPWM_HAL_GENERATOR_MODE_FORCE_LOW : channel->duty == 100 ? in mcpwm_esp32_duty_set()
111 channel->duty / 100; in mcpwm_esp32_duty_set()
250 channel->duty = (uint32_t)duty_cycle; in mcpwm_esp32_set_cycles()
/Zephyr-Core-3.6.0/dts/bindings/pwm/
Dnxp,s32-emios-pwm.yaml22 duty-cycle = <32768>;
30 duty-cycle = <32768>;
39 duty-cycle = <32768>;
102 - OPWFMB: provides waveforms with variable duty cycle and frequency,
135 duty-cycle:
138 Duty-cycle (in ticks) for PWM channel at boot time.
Dinfineon,xmc4xxx-ccu8-pwm.yaml63 signal can, for example, be used as PWM, but note that the duty cycle of the
64 low signal will be (1 - duty) as set via the API.
68 duty cycle and high/low dead times. But the pulse duration applies to
/Zephyr-Core-3.6.0/dts/bindings/sensor/
Dvishay,vcnl4040.yaml36 led-duty-cycle:
40 description: LED duty cycle in Hz
/Zephyr-Core-3.6.0/drivers/led/
Dled_mchp_xec.c118 /* return duty cycle scaled to [0, 255]
129 * BBLED blinking mode uses an 8-bit accumulator and an 8-bit duty cycle
130 * register. The duty cycle register is programmed once and the
134 * 8-bit duty cycle values: 0x00 = full off, 0xff = full on.
138 * duty_cycle in [0, 1]. Register value for duty cycle is
/Zephyr-Core-3.6.0/boards/arm/mr_canhubk3/
Dmr_canhubk3.dts491 duty-cycle = <0>;
500 duty-cycle = <0>;
509 duty-cycle = <0>;
518 duty-cycle = <0>;
527 duty-cycle = <0>;
536 duty-cycle = <0>;
544 duty-cycle = <0>;
583 duty-cycle = <0>;
591 duty-cycle = <0>;
/Zephyr-Core-3.6.0/drivers/i2c/
Di2c_lpc11u6x.h61 volatile uint32_t sclh; /* SCL Duty Cycle */
62 volatile uint32_t scll; /* SCL Duty Cycle */
/Zephyr-Core-3.6.0/samples/sensor/vcnl4040/boards/
Dadafruit_feather_stm32f405.overlay13 led-duty-cycle = <320>;
/Zephyr-Core-3.6.0/drivers/led_strip/
DKconfig.lpd880x13 duty cycle can be set at 7 bit resolution via a
/Zephyr-Core-3.6.0/tests/drivers/pwm/pwm_loopback/boards/
Dmr_canhubk3.overlay36 /delete-property/ duty-cycle;
/Zephyr-Core-3.6.0/samples/sensor/sgp40_sht4x/
DKconfig17 Maximum duty cycle for using the heater is 5%
/Zephyr-Core-3.6.0/dts/riscv/
Driscv32-litex-vexriscv.dtsi266 litex,clock-duty-num = <1>;
267 litex,clock-duty-den = <2>;
279 litex,clock-duty-num = <1>;
280 litex,clock-duty-den = <2>;
/Zephyr-Core-3.6.0/dts/bindings/i3c/
Dnxp,mcux-i3c.yaml46 so that open drain clock is 50% duty cycle.
/Zephyr-Core-3.6.0/samples/drivers/led_xec/src/
Dmain.c80 LOG_INF("blink: T = 0.5 second, duty cycle = 0.5"); in led_test()
92 LOG_INF("blink: T = 3 seconds, duty cycle = 0.4"); in led_test()

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