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/Zephyr-Core-3.5.0/dts/bindings/clock/
Dst,stm32-lse-clock.yaml11 driving-capability:
15 LSE driving capability, within the range 0 to 3.
16 0 represents the lowests driving capability, 3
/Zephyr-Core-3.5.0/drivers/spi/
DKconfig.rpi_pico11 Enable driving SPI via PIO on the PICO
/Zephyr-Core-3.5.0/dts/bindings/watchdog/
Dnxp,fs26-wdog.yaml15 The FS26 uses a 32-bit SPI interface. The MCU is the primary driving MOSI and
16 FS26 is the secondary driving MISO. Therefore the FS26 devicetree node must be
/Zephyr-Core-3.5.0/dts/bindings/display/
Dsolomon,ssd16xx-common.yaml75 description: Gate driving voltage values
79 description: Source driving voltage values
Dlcd-controller.yaml4 # Common fields for LCD controllers driving a panel.
/Zephyr-Core-3.5.0/samples/basic/servo_motor/dts/bindings/
Dpwm-servo.yaml14 description: PWM specifier driving the servo motor.
/Zephyr-Core-3.5.0/drivers/gpio/
DKconfig.mmio3212 driving an LED, or chip-select line for an SPI device.
Dgpio_mmio32.c15 * expects to be specified using a GPIO pin, e.g. for driving an LED, or
/Zephyr-Core-3.5.0/dts/bindings/sensor/
Dst,vl53l1x.yaml14 Driving the XSHUT pin low puts the VL53L1X into hardware
/Zephyr-Core-3.5.0/samples/boards/nrf/nrf_led_matrix/
DREADME.rst18 of GPIOs available for driving a LED matrix. To do it, one needs to add an
/Zephyr-Core-3.5.0/dts/bindings/spi/
Dmicrochip,xec-qmspi.yaml58 description: Delay in system clocks from CS# de-assertion to driving HOLD# and WP#
Dmicrochip,xec-qmspi-ldma.yaml71 Delay in QMSPI main clocks from CS# de-assertion to driving HOLD#
/Zephyr-Core-3.5.0/dts/bindings/pinctrl/
Dnuvoton,numaker-pinctrl.yaml73 Set the driving strength of a pin. Hardware default configuration is low and
Drenesas,rcar-pfc.yaml10 as driving ability.
Dpincfg-node.yaml105 enable output on a pin without actively driving it (e.g. enable an output
Datmel,sam0-pinctrl.yaml64 - output-enable: Enable output on a pin without actively driving it.
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/sam3x/
DKconfig.soc42 thus driving the processor clock.
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/sam4e/
DKconfig.soc44 thus driving the processor clock.
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/sam4s/
DKconfig.soc64 thus driving the processor clock.
/Zephyr-Core-3.5.0/drivers/display/
Dssd1306_regs.h81 * Timing and Driving Scheme Setting Command Table
/Zephyr-Core-3.5.0/drivers/serial/
Duart_stm32.h32 /* clock subsystem driving this peripheral */
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/same70/
DKconfig.soc95 thus driving the processor clock.
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/samv71/
DKconfig.soc96 thus driving the processor clock.
/Zephyr-Core-3.5.0/dts/bindings/gpio/
Dnordic,nrf-gpio-forwarder.yaml13 core is responsible for configuring the pins and driving them as needed.
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec1501/
Dpower.c33 * If a JTAG/SWD debug probe is connected driving TRST# high and

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