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/Zephyr-latest/dts/bindings/spi/
Dnxp,imx-flexspi.yaml1 # Copyright 2018-2023, NXP
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,imx-flexspi"
8 include: [spi-controller.yaml, pinctrl-device.yaml]
17 ahb-bufferable:
23 ahb-cacheable:
29 ahb-prefetch:
34 ahb-read-addr-opt:
40 combination-mode:
43 Combine port A and port B data pins to support octal mode access by
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/Zephyr-latest/dts/bindings/mspi/
Dmspi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
8 on-bus: mspi
14 mspi-max-frequency:
22 mspi-io-mode:
25 - "MSPI_IO_MODE_SINGLE"
26 - "MSPI_IO_MODE_DUAL"
27 - "MSPI_IO_MODE_DUAL_1_1_2"
28 - "MSPI_IO_MODE_DUAL_1_2_2"
29 - "MSPI_IO_MODE_QUAD"
30 - "MSPI_IO_MODE_QUAD_1_1_4"
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Dmspi-controller.yaml2 # SPDX-License-Identifier: Apache-2.0
11 clock-frequency:
15 "#address-cells":
18 "#size-cells":
22 op-mode:
25 - "MSPI_CONTROLLER"
26 - "MSPI_PERIPHERAL"
34 - "MSPI_HALF_DUPLEX"
35 - "MSPI_FULL_DUPLEX"
41 dqs-support:
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/Zephyr-latest/tests/drivers/mspi/flash/boards/
Dnative_sim.overlay4 * SPDX-License-Identifier: Apache-2.0
15 ce-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>,
17 dqs-support;
18 software-multiperipheral;
22 compatible = "zephyr,mspi-emul-flash";
25 mspi-max-frequency = <48000000>;
26 mspi-io-mode = "MSPI_IO_MODE_QUAD";
27 mspi-data-rate = "MSPI_DATA_RATE_SINGLE";
28 mspi-hardware-ce-num = <0>;
29 read-command = <0x0B>;
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/Zephyr-latest/doc/hardware/peripherals/
Dmspi.rst3 Multi-bit SPI Bus
6 The MSPI (multi-bit SPI) is provided as a generic API to accommodate
16 .. _mspi-controller-api:
21 Zephyr's MSPI controller API may be used when a multi-bit SPI controller
25 not limited to high-speed, high density flash/psram memory devices, displays
30 The relationship between the controller and device drivers is many-to-many to
57 to re-initialize the hardware with new parameters during runtime.
99 whether to support scatter IO and callback management. The controller can determine
112 The mspi controller's bindings should reference mspi-controller.yaml as one of the base.
114 .. code-block:: devicetree
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/Zephyr-latest/include/zephyr/drivers/
Dmspi.h4 * SPDX-License-Identifier: Apache-2.0
235 /** @brief DQS support flag */
241 /** @brief GPIO chip-select line numbers (optional) */
247 /** @brief Whether to re-initialize controller */
279 /** @brief Configure DQS mode */
528 * re-initialize their controller hardware. Additional SoC platform specific
530 * binding(xxx,mspi-controller.yaml) so that one may derive the settings from
532 * change during run-time. The bindings for @see mspi_cfg can be found in
533 * mspi-controller.yaml.
538 * @retval -EIO General input / output error, failed to configure device.
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/Zephyr-latest/doc/releases/
Drelease-notes-3.7.rst10 This release is the last non-maintenance 3.x release and, as such, will be the next
11 :ref:`Long Term Support (LTS) release <release_process_lts>`.
18 * A long-awaited :ref:`HTTP Server <http_server_interface>` library, and associated service API,
20 statically or dynamically, and WebSocket support is included.
21 * :ref:`POSIX support <posix_support>` has been extended, with most Options of the IEEE 1003-2017
22 :ref:`System Interfaces <posix_system_interfaces_required>` receiving support, as well as most
25 * Bluetooth Host has been extended with support for the Nordic UART Service (NUS), Hands-free Audio
29 :ref:`read-then-decode approach <sensor-read-and-decode>` that enables more types of sensors and
35 * Trusted Firmware-M (TF-M) 2.1.0 and Mbed TLS 3.6.0 have been integrated into Zephyr.
39 1588) allows to synchronize time across devices with sub-microsecond accuracy.
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/Zephyr-latest/drivers/mspi/
Dmspi_ambiq_ap3.c4 * SPDX-License-Identifier: Apache-2.0
91 LOG_INST_ERR(cfg->log, "%u,Frequency not supported!", __LINE__); in mspi_set_freq()
105 LOG_INST_ERR(cfg->log, "%u, incorrect data rate, only SDR is supported.", __LINE__); in mspi_set_line()
188 if (ctx->owner) { in mspi_context_ce_control()
189 if (ctx->xfer.hold_ce && in mspi_context_ce_control()
190 ctx->xfer.ce_sw_ctrl.gpio.port != NULL) { in mspi_context_ce_control()
192 gpio_pin_set_dt(&ctx->xfer.ce_sw_ctrl.gpio, 1); in mspi_context_ce_control()
193 k_busy_wait(ctx->xfer.ce_sw_ctrl.delay); in mspi_context_ce_control()
195 k_busy_wait(ctx->xfer.ce_sw_ctrl.delay); in mspi_context_ce_control()
196 gpio_pin_set_dt(&ctx->xfer.ce_sw_ctrl.gpio, 0); in mspi_context_ce_control()
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/Zephyr-latest/boards/nxp/mimxrt1024_evk/doc/
Dindex.rst7 high-performance feature set in low-cost LQFP packages, further simplifying
9 Cortex®-M7 core at 500 MHz.
14 - MIMXRT1024DAG5A MCU (600 MHz, 256 KB on-chip memory, 4096KB on-chip QSPI
17 - Memory
19 - 256 Mbit SDRAM
20 - 32 Mbit QSPI Flash
21 - TF socket for SD card
23 - Connectivity
25 - 10/100 Mbit/s Ethernet PHY
26 - Micro USB host and OTG connectors
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