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/Zephyr-Core-3.5.0/dts/bindings/gpio/
Dxlnx,xps-gpio-1.00.a.yaml3 compatible: "xlnx,xps-gpio-1.00.a"
5 include: [gpio-controller.yaml, base.yaml]
7 bus: xlnx,xps-gpio-1.00.a
10 # https://github.com/Xilinx/device-tree-xlnx
16 xlnx,all-inputs:
21 xlnx,all-outputs:
26 xlnx,dout-default:
29 Default output value. If n-th bit is 1, GPIO-n default value is 1.
31 xlnx,gpio-width:
36 xlnx,tri-default:
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/Zephyr-Core-3.5.0/boards/arm/arty/dts/
Darty_a7_arm_designstart.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 zephyr,shell-uart = &uartlite0;
16 /* Use DTCM as SRAM by default */
29 spi-flash0 = &flash0;
33 compatible = "gpio-leds";
35 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
95 gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
105 compatible = "gpio-keys";
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/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_xlnx_axi.c4 * SPDX-License-Identifier: Apache-2.0
53 uint32_t dout; member
60 /* Workaround to handle channel 2 interrupts from channel 1*/
67 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_read_data()
69 return sys_read32(config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_read_data()
74 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_write_data()
76 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_write_data()
81 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_write_tri()
83 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_TRI_OFFSET); in gpio_xlnx_axi_write_tri()
88 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_pin_configure()
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/Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/common/
DKconfig.soc2 # SPDX-License-Identifier: Apache-2.0
16 bool "Support for external, SPI-connected RAM"
23 default 8192
34 default y
42 default 262134 if SYS_HEAP_SMALL_ONLY
43 default 1048576 if !SYS_HEAP_SMALL_ONLY
53 default SPIRAM_MODE_QUAD
63 default SPIRAM_TYPE_ESPPSRAM16
66 bool "ESP-PSRAM16 or APS1604"
69 bool "ESP-PSRAM32 or IS25WP032"
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/Zephyr-Core-3.5.0/drivers/usb/udc/
Dudc_kinetis.c5 * SPDX-License-Identifier: Apache-2.0
31 #define USBFSOTG_BD_NINC BIT(2)
59 uint32_t reserved_1_0 : 2;
68 uint32_t reserved_1_0 : 2;
125 struct net_buf *out_buf[2];
126 bool busy[2];
137 const struct usbfsotg_config *config = dev->config; in usbfsotg_get_ebd()
140 bd_idx = USB_EP_GET_IDX(cfg->addr) * 4U + (cfg->stat.odd ^ opposite); in usbfsotg_get_ebd()
141 if (USB_EP_DIR_IS_IN(cfg->addr)) { in usbfsotg_get_ebd()
142 bd_idx += 2U; in usbfsotg_get_ebd()
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/Zephyr-Core-3.5.0/drivers/adc/
Dadc_lmp90xxx.c4 * SPDX-License-Identifier: Apache-2.0
53 #define LMP90XXX_REG_CH_INPUTCN(ch) (0x20U + (2 * ch))
54 #define LMP90XXX_REG_CH_CONFIG(ch) (0x21U + (2 * ch))
57 #define LMP90XXX_URA(addr) ((addr >> 4U) & GENMASK(2, 0))
64 /* LMP90xxx instruction byte 2 (INST2) */
75 #define LMP90XXX_PWRCN(x) (x & BIT_MASK(2))
79 #define LMP90XXX_DRDYB_AFT_CRC(x) ((x & BIT(0)) << 2)
80 #define LMP90XXX_CH_SCAN_SEL(x) ((x & BIT_MASK(2)) << 6)
102 /* Default Output Data Rate (ODR) is 214.65 SPS */
106 #define LMP90XXX_HAS_DRDYB(config) (config->drdyb.port != NULL)
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/Zephyr-Core-3.5.0/drivers/usb/device/
Dusb_dc_sam_usbc.c4 * SPDX-License-Identifier: Apache-2.0
102 static struct sam_usbc_desc_table dev_desc[(NUM_OF_EP_MAX + 1) * 2];
110 "DOUT",
118 static uint32_t dev_ep_sta_dbg[2][NUM_OF_EP_MAX];
122 if (regs->UESTA[ep_idx] != dev_ep_sta_dbg[0][ep_idx]) { in usb_dc_sam_usbc_isr_sta_dbg()
123 dev_ep_sta_dbg[0][ep_idx] = regs->UESTA[ep_idx]; in usb_dc_sam_usbc_isr_sta_dbg()
128 regs->UDCON, regs->UDINT, regs->UDINTE, in usb_dc_sam_usbc_isr_sta_dbg()
129 regs->UECON[ep_idx], regs->UESTA[ep_idx], in usb_dc_sam_usbc_isr_sta_dbg()
136 regs->UDCON, regs->UDINT, regs->UDINTE, in usb_dc_sam_usbc_isr_sta_dbg()
137 regs->UECON[ep_idx], regs->UESTA[ep_idx]); in usb_dc_sam_usbc_isr_sta_dbg()
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