dma (full) in projects: hal_espressif-latest

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/hal_espressif-latest/components/esp_hw_support/include/esp_private/
D	gdma.h	33 …gdma_channel_handle_t sibling_chan; /!< DMA sibling channel handle (NULL means having sibling is … 34 gdma_channel_direction_t direction; /!< DMA channel direction / 36 …int reserve_sibling: 1; /!< If set, DMA channel allocator would prefer to allocate new channel in… 44 …* Actually the GDMA driver has no knowledge about the DMA buffer (address and size) used by … 49 …size_t sram_trans_align; /!< DMA transfer alignment for memory in SRAM, in bytes. The driver ena… 50 …size_t psram_trans_align; /!< DMA transfer alignment for memory in PSRAM, in bytes. The driver se… 100 gdma_trigger_peripheral_t periph; /!< Target peripheral which will trigger DMA operations / 118 …bool owner_check; /!< If set / clear, DMA channel enables / disables checking owner validity… 119 …bool auto_update_desc; /!< If set / clear, DMA channel enables / disables hardware to update desc… 130 * - ESP_OK: Create DMA channel successfully [all …]
/hal_espressif-latest/components/hal/include/hal/
D	spi_slave_hd_hal.h	29 * - To send data through DMA, call `spi_slave_hd_hal_txdma` 33 * - To receive data through DMA, call `spi_slave_hd_hal_rxdma` 52 * @brief Type of dma descriptor with appended members 53 …* this structure inherits DMA descriptor, with a pointer to the transaction descriptor pass… 56 lldesc_t desc; ///< DMA descriptor 63 …spi_dma_dev_t dma_in; ///< Input DMA(DMA -> RAM) peripheral register ad… 64 …spi_dma_dev_t dma_out; ///< Output DMA(RAM -> DMA) peripheral register ad… 65 bool dma_enabled; ///< DMA enabled or not 66 uint32_t tx_dma_chan; ///< TX DMA channel used. 67 uint32_t rx_dma_chan; ///< RX DMA channel used. [all …]
D	spi_slave_hal.h	17 // 2. initialize the DMA descriptors if DMA used 23 // 8. check and reset the DMA (if needed) before the next transaction 39 …spi_dma_dev_t dma_in; ///< Address of the DMA peripheral registers which stores the data… 40 …spi_dma_dev_t dma_out; ///< Address of the DMA peripheral registers which transmits the d… 42 lldesc_t dmadesc_rx; /< Array of DMA descriptor used by the TX DMA. 46 lldesc_t dmadesc_tx; /*< Array of DMA descriptor used by the RX DMA. 51 uint32_t tx_dma_chan; ///< TX DMA channel 52 uint32_t rx_dma_chan; ///< RX DMA channel 79 spi_dma_dev_t dma_in; ///< Input DMA(DMA -> RAM) peripheral register address 80 spi_dma_dev_t *dma_out; ///< Output DMA(RAM -> DMA) peripheral register address [all …]
D	spi_hal.h	17 // 2. initialize the DMA descriptors if DMA used 64 * DMA configuration structure 68 spi_dma_dev_t dma_in; ///< Input DMA(DMA -> RAM) peripheral register address 69 spi_dma_dev_t dma_out; ///< Output DMA(RAM -> DMA) peripheral register address 70 …bool dma_enabled; ///< Whether the DMA is enabled, do not update after initializ… 71 lldesc_t dmadesc_tx; /< Array of DMA descriptor used by the TX DMA. 75 lldesc_t dmadesc_rx; /*< Array of DMA descriptor used by the RX DMA. 79 uint32_t tx_dma_chan; ///< TX DMA channel 80 uint32_t rx_dma_chan; ///< RX DMA channel 107 lldesc_t dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA. [all …]
D	adc_hal.h	23 //ADC utilises SPI3 DMA on ESP32S2 28 //ADC utilises I2S0 DMA on ESP32 45 * @brief Enum for DMA descriptor status 48 ADC_HAL_DMA_DESC_VALID = 0, ///< This DMA descriptor is written by HW already 49 ADC_HAL_DMA_DESC_WAITING = 1, ///< This DMA descriptor is not written by HW yet 50 ADC_HAL_DMA_DESC_NULL = 2 ///< This DMA descriptor is NULL 57 void dev; ///< DMA peripheral address 58 uint32_t eof_desc_num; ///< Number of dma descriptors that is eof 60 uint32_t dma_chan; ///< DMA channel to be used 69 dma_descriptor_t rx_desc; ///< DMA descriptors [all …]
D	adc_types.h	66 * @brief ADC digital controller (DMA mode) work mode. 76 * @brief ADC digital controller (DMA mode) output data format option. 125 * @brief ADC digital controller (DMA mode) output data format. 126 * Used to analyze the acquired ADC (DMA) data. 127 * @note ESP32: Only `type1` is valid. ADC2 does not support DMA mode. 150 * @brief ADC digital controller (DMA mode) output data format. 151 * Used to analyze the acquired ADC (DMA) data. 170 * @brief ADC digital controller (DMA mode) output data format. 171 * Used to analyze the acquired ADC (DMA) data. 190 * @brief ADC digital controller (DMA mode) output data format. [all …]
D	sdio_slave_hal.h	51 1. Call `sdio_slave_hal_recv_start` to start the receiving DMA. 63 When the DMA is started, the descriptors is loaded onto the DMA linked-list, and the 78 the DMA is stopped. 82 the DMA is stopped. 86 DMA is not stopped. 93 1. Call `sdio_slave_hal_send_start` to start the sending DMA. 115 … to get all buffers queued, regardless sent or not. Don't do this when the DMA is not stopped. 118 … but not sent buffers if you want to reset the counter only. Don't do this when the DMA is not 172 /// DMA descriptor with extra fields 259 * The hardware sending DMA starts. If there is existing data, send them. [all …]
/hal_espressif-latest/components/soc/esp32/include/soc/
D	emac_dma_struct.h	26 …uint32_t sw_rst : 1; /When this bit is set the MAC DMA Controller resets the logic and a… 28 …LEN) value is equal to zero the descriptor table is taken as contiguous by the DMA in Ring mode./ 30 …/These bits indicate the maximum number of beats to be transferred in one DMA transaction. If the… 31 …riority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits ar… 33 …o be transferred in one Rx DMA transaction. This is the maximum value that is used in a single blo… 34 …DMA to use the value configured in Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable o… 35 …grammed PBL value (Bits[22:17] and Bits[13:8]) eight times. Therefore the DMA transfers the data … 45 …uint32_t dmatxpolldemand; /When these bits are written with any value the DMA reads the current … 46 …DMA reads the current descriptor to which the Current Host Receive Descriptor Register is pointing… 47 …ist. The LSB Bits[1:0] are ignored and internally taken as all-zero by the DMA. Therefore these LS… [all …]
D	uhci_struct.h	28 uint32_t ahbm_fifo_rst: 1; /Set this bit to reset dma ahb fifo./ 29 … uint32_t ahbm_rst: 1; /Set this bit to reset dma ahb interface./ 34 … /Set this bit to produce eof after DMA pops all data clear this bit to produce eof af… 38 …uint32_t outdscr_burst_en: 1; /Set this bit to enable DMA in links to use burst … 39 …uint32_t indscr_burst_en: 1; /Set this bit to enable DMA out links to use burst… 40 uint32_t out_data_burst_en: 1; /Set this bit to enable DMA burst MODE/ 57 …uint32_t tx_start: 1; /when DMA detects a separator char it will produce… 58 …uint32_t rx_hung: 1; /when DMA takes a lot of time to receive a data … 59 …uint32_t tx_hung: 1; /when DMA takes a lot of time to read a data from … 67 …scr_empty: 1; /*when there are not enough in links for DMA it will produce uhc… [all …]
/hal_espressif-latest/components/hal/esp32c2/include/hal/
D	gdma_ll.h	46 * @brief Enable DMA clock gating 55 * @brief Get DMA RX channel interrupt status word 64 * @brief Enable DMA RX channel interrupt 76 * @brief Clear DMA RX channel interrupt 85 * @brief Get DMA RX channel interrupt status register address 93 * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default 101 * @brief Enable DMA RX channel burst reading data, disabled by default 109 * @brief Enable DMA RX channel burst reading descriptor link, disabled by default 117 * @brief Reset DMA RX channel FSM and FIFO pointer 127 * @brief Check if DMA RX FIFO is full [all …]
/hal_espressif-latest/components/hal/esp32c3/include/hal/
D	gdma_ll.h	46 * @brief Enable DMA clock gating 55 * @brief Get DMA RX channel interrupt status word 64 * @brief Enable DMA RX channel interrupt 76 * @brief Clear DMA RX channel interrupt 85 * @brief Get DMA RX channel interrupt status register address 93 * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default 101 * @brief Enable DMA RX channel burst reading data, disabled by default 109 * @brief Enable DMA RX channel burst reading descriptor link, disabled by default 117 * @brief Reset DMA RX channel FSM and FIFO pointer 127 * @brief Check if DMA RX FIFO is full [all …]
/hal_espressif-latest/components/hal/esp32s3/include/hal/
D	gdma_ll.h	59 * @brief Enable DMA clock gating 68 * @brief Get DMA RX channel interrupt status word 77 * @brief Enable DMA RX channel interrupt 89 * @brief Clear DMA RX channel interrupt 98 * @brief Get DMA RX channel interrupt status register address 106 * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default 114 * @brief Enable DMA RX channel burst reading data, disabled by default 122 * @brief Enable DMA RX channel burst reading descriptor link, disabled by default 130 * @brief Reset DMA RX channel FSM and FIFO pointer 140 * @brief Set DMA RX channel memory block size [all …]
/hal_espressif-latest/components/hal/esp32c6/include/hal/
D	gdma_ll.h	93 * @brief Enable DMA clock gating 102 * @brief Get DMA RX channel interrupt status word 111 * @brief Enable DMA RX channel interrupt 123 * @brief Clear DMA RX channel interrupt 132 * @brief Get DMA RX channel interrupt status register address 140 * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default 148 * @brief Enable DMA RX channel burst reading data, disabled by default 156 * @brief Enable DMA RX channel burst reading descriptor link, disabled by default 164 * @brief Reset DMA RX channel FSM and FIFO pointer 174 * @brief Check if DMA RX FIFO is full [all …]
/hal_espressif-latest/components/hal/esp32h2/include/hal/
D	gdma_ll.h	93 * @brief Enable DMA clock gating 102 * @brief Get DMA RX channel interrupt status word 111 * @brief Enable DMA RX channel interrupt 123 * @brief Clear DMA RX channel interrupt 132 * @brief Get DMA RX channel interrupt status register address 140 * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default 148 * @brief Enable DMA RX channel burst reading data, disabled by default 156 * @brief Enable DMA RX channel burst reading descriptor link, disabled by default 164 * @brief Reset DMA RX channel FSM and FIFO pointer 174 * @brief Check if DMA RX FIFO is full [all …]
/hal_espressif-latest/components/mbedtls/port/sha/dma/
D	sha.c	73 * * Must be in DMA capable memory, so stack is not a safe place to put them 74 * * To avoid having to malloc/free them for every DMA operation 120 /* Enable SHA and DMA hardware / in esp_sha_acquire_hardware() 131 / Disable SHA and DMA hardware / in esp_sha_release_hardware() 184 / Hash the input block by block, using non-DMA mode / 212 / Performs SHA on multiple blocks at a time using DMA 213 splits up into smaller operations for inputs that exceed a single DMA list 222 ESP_LOGE(TAG, "SHA DMA buf_len cannot exceed max size for a single block"); in esp_sha_dma() 226 /* DMA cannot access memory in flash, hash block by block instead of using DMA / in esp_sha_dma() 241 / Copy to internal buf if buf is in non DMA capable memory */ in esp_sha_dma() [all …]
/hal_espressif-latest/components/hal/esp32/include/hal/
D	spi_ll.h	53 … ESP32-S2 and earlier chips, DMA registers are part of SPI registers. So set the registers of SPI … 169 * Reset SPI DMA FIFO 179 * Reset SPI DMA TX FIFO 192 * Reset SPI DMA RX FIFO 225 * SPI configuration for DMA 229 * Enable/Disable RX DMA (Peripherals->DMA->RAM) 240 * Enable/Disable TX DMA (RAM->DMA->Peripherals) 251 * Configuration of RX DMA EOF interrupt generation way 254 …_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_b… 375 //The timing needs to be fixed to meet the requirements of DMA in spi_ll_slave_set_mode() [all …]
/hal_espressif-latest/components/driver/spi/include/driver/
D	spi_common.h	22 //Maximum amount of bytes that can be put in one DMA descriptor 69 * @brief SPI DMA channels 72 SPI_DMA_DISABLED = 0, ///< Do not enable DMA for SPI 74 SPI_DMA_CH1 = 1, ///< Enable DMA, select DMA Channel 1 75 SPI_DMA_CH2 = 2, ///< Enable DMA, select DMA Channel 2 77 SPI_DMA_CH_AUTO = 3, ///< Enable DMA, channel is automatically selected by driver 118 …nsfer size, in bytes. Defaults to 4092 if 0 when DMA enabled, or to `SOC_SPI_MAXIMUM_BUFFER_SIZE` … 136 …* @param dma_chan - Selecting a DMA channel for an SPI bus allows transactions on the bus wit… 139 * - Set to SPI_DMA_CH_AUTO to let the driver to allocate the DMA channel. 141 …* @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated … [all …]
D	spi_slave_hd.h	28 uint8_t* data; ///< Buffer to send, must be DMA capable 53 … cb_send_dma_ready; ///< Callback when TX data buffer is loaded to the hardware (DMA) 55 … cb_recv_dma_ready; ///< Callback when RX data buffer is loaded to the hardware (DMA) 67 … (1<<2) ///< Adopt DMA append mode for transactions. In this mode, users can load(append) DMA de… 83 spi_dma_chan_t dma_chan; ///< DMA channel to used. 97 * - ESP_ERR_NOT_FOUND if there is no available DMA channel 124 * - The buffer given is not DMA capable 172 …* @note In this mode, user transaction descriptors will be appended to the DMA and the DMA will ke… 181 * - The buffer given is not DMA capable
/hal_espressif-latest/components/hal/esp32s2/include/hal/
D	spi_ll.h	55 … ESP32-S2 and earlier chips, DMA registers are part of SPI registers. So set the registers of SPI … 61 SPI_LL_INTR_IN_SUC_EOF = BIT(1), ///< DMA in_suc_eof triggered 62 SPI_LL_INTR_OUT_EOF = BIT(2), ///< DMA out_eof triggered 63 SPI_LL_INTR_OUT_TOTAL_EOF = BIT(3), ///< DMA out_total_eof triggered 64 SPI_LL_INTR_IN_FULL = BIT(4), ///< DMA in_full error happened 65 SPI_LL_INTR_OUT_EMPTY = BIT(5), ///< DMA out_empty error happened 158 // Configure DMA In-Link to not be terminated when transaction bit counter exceeds in spi_ll_slave_init() 254 * Reset SPI DMA TX FIFO 267 * Reset SPI DMA RX FIFO 302 * SPI configuration for DMA [all …]
D	cp_dma_hal.h	`13 // CP DMA HAL usages: 15 // 2. Enable DMA and interrupt by cp_dma_hal_start 17 // 4. Restart the DMA engine in case it's not in working 61 * @brief Start mem2mem DMA state machine 66 * @brief Stop mem2mem DMA state machine 86 …* @brief Give the owner of descriptors between [start_desc, end_desc] to DMA, and restart DMA HW e…`
/hal_espressif-latest/components/soc/esp32s3/include/soc/
D	periph_defs.h	101 ETS_SPI2_DMA_INTR_SOURCE, /*< interrupt of SPI2 DMA, level/ 102 ETS_SPI3_DMA_INTR_SOURCE, /*< interrupt of SPI3 DMA, level/ 123 ETS_DMA_IN_CH0_INTR_SOURCE, /*< interrupt of general DMA RX channel 0, LEVEL/ 124 ETS_DMA_IN_CH1_INTR_SOURCE, /*< interrupt of general DMA RX channel 1, LEVEL/ 125 ETS_DMA_IN_CH2_INTR_SOURCE, /*< interrupt of general DMA RX channel 2, LEVEL/ 126 ETS_DMA_IN_CH3_INTR_SOURCE, /*< interrupt of general DMA RX channel 3, LEVEL/ 127 ETS_DMA_IN_CH4_INTR_SOURCE, /*< interrupt of general DMA RX channel 4, LEVEL/ 128 ETS_DMA_OUT_CH0_INTR_SOURCE, /*< interrupt of general DMA TX channel 0, LEVEL/ 129 ETS_DMA_OUT_CH1_INTR_SOURCE, /*< interrupt of general DMA TX channel 1, LEVEL/ 130 ETS_DMA_OUT_CH2_INTR_SOURCE, /*< interrupt of general DMA TX channel 2, LEVEL/ [all …]
/hal_espressif-latest/components/mbedtls/port/aes/dma/include/
D	esp_aes_dma_priv.h	`18 * @brief Start the DMA engine 23 * - ESP_OK: Successfully started the DMA 24 * - ESP_ERR_INVALID_STATE: No DMA channel available 29 * @brief Check if the DMA engine is finished reading the result 33 * - true: DMA finished 34 * - false: DMA not yet finished`
/hal_espressif-latest/components/driver/include/esp_private/
D	spi_common_internal.h	66 bool dma_enabled; ///< To enable DMA or not 67 …int tx_dma_chan; ///< TX DMA channel, on ESP32 and ESP32S2, tx_dma_chan and rx_dma_chan… 68 …int rx_dma_chan; ///< RX DMA channel, on ESP32 and ESP32S2, tx_dma_chan and rx_dma_chan… 69 int dma_desc_num; ///< DMA descriptor number of dmadesc_tx or dmadesc_rx. 70 lldesc_t dmadesc_tx; ///< DMA descriptor array for TX 71 lldesc_t dmadesc_rx; ///< DMA descriptor array for RX 113 * @brief Alloc DMA for SPI 116 * @param dma_chan DMA channel to be used 117 …* @param[out] out_actual_tx_dma_chan Actual TX DMA channel (if you choose to assign a specific DM… 118 …* @param[out] out_actual_rx_dma_chan Actual RX DMA channel (if you choose to assign a specific DM… [all …]
/hal_espressif-latest/components/driver/deprecated/
D	i2s_legacy.c	85 * @brief DMA buffer object 106 uint32_t last_buf_size; /!< DMA last buffer size / 107 i2s_dma_t tx; /!< DMA Tx buffer/ 108 i2s_dma_t rx; /!< DMA Rx buffer/ 156 I2S DMA operation 242 ESP_EARLY_LOGE(TAG, "dma error, interrupt status: 0x%08x", status); in i2s_intr_handler_default() 333 …OR(gdma_new_channel(&dma_cfg, &p_i2s[i2s_num]->tx_dma_chan), TAG, "Register tx dma channel error"); in i2s_dma_intr_init() 334 …ESP_RETURN_ON_ERROR(gdma_connect(p_i2s[i2s_num]->tx_dma_chan, trig), TAG, "Connect tx dma channel … in i2s_dma_intr_init() 342 …OR(gdma_new_channel(&dma_cfg, &p_i2s[i2s_num]->rx_dma_chan), TAG, "Register rx dma channel error"); in i2s_dma_intr_init() 343 …ESP_RETURN_ON_ERROR(gdma_connect(p_i2s[i2s_num]->rx_dma_chan, trig), TAG, "Connect rx dma channel … in i2s_dma_intr_init() [all …]
/hal_espressif-latest/components/driver/deprecated/driver/
D	i2s.h	134 * @brief Write data to I2S DMA transmit buffer. 145 * many ticks pass without space becoming available in the DMA 147 * data is written to the DMA buffer in pieces, the overall operation 158 …* @brief Write data to I2S DMA transmit buffer while expanding the number of bits per sample. For … 173 * many ticks pass without space becoming available in the DMA 175 * data is written to the DMA buffer in pieces, the overall operation 189 * @brief Read data from I2S DMA receive buffer 199 …bytes becoming available in the DMA receive buffer, then the function will return (note that if da… 258 * @brief Zero the contents of the TX DMA buffer. 260 * Pushes zero-byte samples into the TX DMA buffer, until it is full. [all …]

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