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Searched +full:dma +full:- +full:pl330 (Results 1 – 6 of 6) sorted by relevance

/Zephyr-latest/dts/bindings/dma/
Darm,dma-pl330.yaml2 # SPDX-License-Identifier: Apache-2.0
5 PL330 DMA Controller
7 A phandle to the DMA controller plus "channel" integer cell specifying
10 Example for pl330 DMA Controller
11 pl330: pl330@48300000 {
12 compatible = "arm,dma-pl330";
14 dma-channels = <8>;
15 #dma-cells = <1>;
18 If PCIe EP client uses channel 0 for Tx DMA and channel 1 for Rx DMA
20 compatible = "brcm,iproc-pcie-ep";
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/Zephyr-latest/dts/common/broadcom/
Dviper-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
17 clock-frequency = <25000000>;
18 reg-shift = <2>;
25 clock-frequency = <100000000>;
26 reg-shift = <2>;
30 pl330: pl330@48300000 { label
31 compatible = "arm,dma-pl330";
34 reg-names = "pl330_regs",
37 dma-channels = <8>;
38 #dma-cells = <1>;
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/Zephyr-latest/drivers/dma/
DKconfig.dma_pl3302 # SPDX-License-Identifier: Apache-2.0
6 prompt "PL330 DMA driver"
10 This option enables support of pl330 DMA Controller.
Ddma_pl330.h4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/dma.h>
17 * Burst length is encoded in following format for pl330
25 * Burst size is encoded in following format for pl330
39 * PL330 works only on 4GB boundary.
40 * PL330 has 32bit registers for source and destination addresses
44 /* PL330 supports max 16MB dma based on AXI bus size */
47 /* Maximum possible values for PL330 ucode loop counters */
61 * transfer sizes, with lesser time out value(10us) DMA channel
Ddma_pl330.c4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/drivers/dma.h>
34 srcbytewidth = BYTE_WIDTH(ch_handle->src_burst_sz); in dma_pl330_get_counter()
35 dstbytewidth = BYTE_WIDTH(ch_handle->dst_burst_sz); in dma_pl330_get_counter()
37 loop_counter = ch_handle->trans_size / in dma_pl330_get_counter()
38 (srcbytewidth * (ch_handle->src_burst_len + 1)); in dma_pl330_get_counter()
40 residue = ch_handle->trans_size - loop_counter * in dma_pl330_get_counter()
41 (srcbytewidth * (ch_handle->src_burst_len + 1)); in dma_pl330_get_counter()
52 int secure = ch_handle->nonsec_mode ? SRC_PRI_NONSEC_VALUE : in dma_pl330_ch_ccr()
55 ccr = ((ch_handle->dst_cache_ctrl & CC_SRCCCTRL_MASK) << in dma_pl330_ch_ccr()
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/Zephyr-latest/dts/arm/intel_socfpga_std/
Dsocfpga.dtsi2 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
28 compatible = "arm,cortex-a9";
31 /* next-level-cache = <&L2>; */ /*cache driver not available yet */
34 compatible = "arm,cortex-a9";
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