| /Zephyr-Core-3.5.0/dts/bindings/dma/ |
| D | st,stm32-dma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller
7 The STM32 DMA is a general-purpose direct memory access controller
8 capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
9 Each stm32 soc with a DMA is of a special version type, which could be
14 compatible: "st,stm32-dma"
16 include: dma-controller.yaml
27 description: If the DMA controller V1 supports memory to memory transfer
29 dma-offset:
32 offset in the table of channels when mapping to a DMAMUX
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| D | st,stm32-bdma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The STM32 BDMA is a general-purpose direct memory access controller
11 described in the dma.txt file, using a four-cell specifier for each
13 1. channel: the bdma stream from 0 to <bdma-requests>
15 3. channel-config: A 32bit mask specifying the BDMA channel configuration
17 -bit 6-7 : Direction (see dma.h)
22 -bit 9 : Peripheral Increment Address
25 -bit 10 : Memory Increment Address
28 -bit 11-12 : Peripheral data size
30 0x1: Half-word (16 bits)
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| D | nxp,mcux-edma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,mcux-edma"
8 include: dma-controller.yaml
14 Specifies base physical address(s) and size of DMA and respective DMAMUX register(s)
15 that routes DMA sources
20 dma-channels:
23 dma-requests:
26 dmamux-reg-offset:
30 The offset value for obtaining DMAMUX register index from DMAMUX channel.
33 channel-gap:
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| D | st,stm32-dmamux.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 capable of supporting independent DMA channels.
9 DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
10 for each dmamux channel: a phandle to the DMA multiplexer plus the following 2 integer cells:
11 1. channel: the mux channel from 0 to <dma-channels> - 1
13 3. channel-config: A 32bit mask specifying the DMA channel configuration
15 -bit 6-7 : Direction (see dma.h)
20 -bit 9 : Peripheral Increment Address
23 -bit 10 : Memory Increment Address
26 -bit 11-12 : Peripheral data size
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| D | st,stm32-dma-v1.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller (V1)
8 This DMA controller includes FIFO control registers.
9 DMA clients connected to the STM32 DMA controller must use the format
10 described in the dma.txt file, using a four-cell specifier for each
11 channel: a phandle to the DMA controller plus the following four integer cells:
12 1. channel: the dma stream from 0 to <dma-requests>
13 2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
14 this value is 0 for Memory-to-memory transfers
15 or a value between <1> .. <dma-generators> (not supported yet)
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| D | gd,gd32-dma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 GD32 DMA controller
9 config: A 32bit mask specifying the DMA channel configuration
10 - bit 6-7: Direction (see dma.h)
11 - 0x0: MEMORY to MEMORY
12 - 0x1: MEMORY to PERIPH
13 - 0x2: PERIPH to MEMORY
14 - 0x3: reserved for PERIPH to PERIPH
16 - bit 9: Peripheral address increase
17 - 0x0: no address increment between transfers
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| D | gd,gd32-dma-v1.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 GD32 DMA controller with FIFO
9 slot: Select peripheral to connect DMA
11 config: A 32bit mask specifying the DMA channel configuration
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
18 - bit 9: Peripheral address increase
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| /Zephyr-Core-3.5.0/dts/bindings/serial/ |
| D | infineon,xmc4xxx-uart.yaml | 3 compatible: "infineon,xmc4xxx-uart"
5 include: [uart-controller.yaml, pinctrl-device.yaml]
11 input-src:
20 - "DX0A"
21 - "DX0B"
22 - "DX0C"
23 - "DX0D"
24 - "DX0E"
25 - "DX0F"
26 - "DX0G"
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/pcie/endpoint/ |
| D | pcie_ep.h | 8 * SPDX-License-Identifier: Apache-2.0
23 PCIE_OB_LOWMEM, /**< PCIe OB window within 32-bit address range */
24 PCIE_OB_HIGHMEM, /**< PCIe OB window above 32-bit address range */
50 * interrupt-safe APIS. Registration of callbacks is done via
60 int (*conf_read)(const struct device *dev, uint32_t offset,
62 void (*conf_write)(const struct device *dev, uint32_t offset,
85 * @param offset Offset within configuration space
86 * @param data Pointer to data read from the offset
92 uint32_t offset, uint32_t *data) in pcie_ep_conf_read() argument
95 (const struct pcie_ep_driver_api *)dev->api; in pcie_ep_conf_read()
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| /Zephyr-Core-3.5.0/dts/arm/st/g4/ |
| D | stm32g431.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32g431", "st,stm32g4", "simple-bus";
13 dma1: dma@40020000 {
15 dma-requests = <6>;
18 dma2: dma@40020400 {
20 dma-requests = <6>;
21 dma-offset = <6>;
25 dma-channels = <12>;
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| D | stm32g491.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32g491", "st,stm32g4", "simple-bus";
14 compatible = "st,stm32-fdcan";
16 reg-names = "m_can", "message_ram";
18 interrupt-names = "LINE_0", "LINE_1";
20 bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>;
21 sample-point = <875>;
22 sample-point-data = <875>;
27 compatible = "st,stm32-timers";
32 interrupt-names = "brk", "up", "trgcom", "cc";
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| /Zephyr-Core-3.5.0/drivers/dma/ |
| D | dma_pl330.c | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/drivers/dma.h>
34 srcbytewidth = BYTE_WIDTH(ch_handle->src_burst_sz); in dma_pl330_get_counter()
35 dstbytewidth = BYTE_WIDTH(ch_handle->dst_burst_sz); in dma_pl330_get_counter()
37 loop_counter = ch_handle->trans_size / in dma_pl330_get_counter()
38 (srcbytewidth * (ch_handle->src_burst_len + 1)); in dma_pl330_get_counter()
40 residue = ch_handle->trans_size - loop_counter * in dma_pl330_get_counter()
41 (srcbytewidth * (ch_handle->src_burst_len + 1)); in dma_pl330_get_counter()
52 int secure = ch_handle->nonsec_mode ? SRC_PRI_NONSEC_VALUE : in dma_pl330_ch_ccr()
55 ccr = ((ch_handle->dst_cache_ctrl & CC_SRCCCTRL_MASK) << in dma_pl330_ch_ccr()
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| D | dma_stm32_bdma.h | 4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/drivers/dma.h>
14 #include <zephyr/drivers/dma/dma_stm32.h>
44 uint8_t offset; /* position in the list of bdmamux channel list */ member
65 bool stm32_bdma_is_irq_active(BDMA_TypeDef *dma, uint32_t id);
69 void stm32_bdma_dump_channel_irq(BDMA_TypeDef *dma, uint32_t id);
70 void stm32_bdma_clear_channel_irq(BDMA_TypeDef *dma, uint32_t id);
71 bool stm32_bdma_is_irq_happened(BDMA_TypeDef *dma, uint32_t id);
72 void stm32_bdma_enable_channel(BDMA_TypeDef *dma, uint32_t id);
73 int stm32_bdma_disable_channel(BDMA_TypeDef *dma, uint32_t id);
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| D | dma_stm32.h | 4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/drivers/dma.h>
43 uint8_t offset; /* position in the list of dmamux channel list */ member
75 bool stm32_dma_is_irq_active(DMA_TypeDef *dma, uint32_t id);
76 bool stm32_dma_is_ht_irq_active(DMA_TypeDef *dma, uint32_t id);
77 bool stm32_dma_is_tc_irq_active(DMA_TypeDef *dma, uint32_t id);
79 void stm32_dma_dump_stream_irq(DMA_TypeDef *dma, uint32_t id);
80 void stm32_dma_clear_stream_irq(DMA_TypeDef *dma, uint32_t id);
81 bool stm32_dma_is_irq_happened(DMA_TypeDef *dma, uint32_t id);
82 bool stm32_dma_is_unexpected_irq_happened(DMA_TypeDef *dma, uint32_t id);
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| /Zephyr-Core-3.5.0/dts/x86/intel/ |
| D | raptor_lake.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/pcie/pcie.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,raptor-lake";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/ |
| D | adsp_shim.h | 4 * SPDX-License-Identifier: Apache-2.0
19 uint32_t dfspsreq; /* Offset: 0x00 */
21 uint32_t dfspsrsp; /* Offset: 0x10 */
23 uint32_t svcfg; /* Offset: 0x18 */
24 uint32_t dfltrc; /* Offset: 0x1c */
37 uint32_t dfpmccap; /* Offset: 0x00 */
40 uint32_t dfhrosccf; /* Offset: 0x04 */
43 uint32_t dfxosccf; /* Offset: 0x08 */
46 uint32_t dflrosccf; /* Offset: 0x0c */
49 uint32_t dfsiorosccf; /* Offset: 0x10 */
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| /Zephyr-Core-3.5.0/tests/drivers/uart/uart_async_api/boards/ |
| D | xmc45_relax_kit.overlay | 1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <zephyr/dt-bindings/dma/infineon-xmc4xxx-dma.h>
6 compatible = "infineon,xmc4xxx-uart";
7 current-speed = <921600>;
8 pinctrl-0 = <&uart_tx_p5_0_u2c0 &uart_rx_p5_1_u2c0>;
9 pinctrl-names = "default";
10 input-src = "DX0G";
12 interrupt-names = "tx", "rx";
14 dma-names = "tx", "rx";
15 fifo-start-offset = <0>;
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| D | xmc47_relax_kit.overlay | 1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <zephyr/dt-bindings/dma/infineon-xmc4xxx-dma.h>
6 compatible = "infineon,xmc4xxx-uart";
9 /delete-property/ scl-src;
10 /delete-property/ sda-src;
12 current-speed = <921600>;
14 interrupt-names = "tx", "rx";
16 dma-names = "tx", "rx";
17 pinctrl-0 = <&uart_tx_p3_15_u1c1 &uart_rx_p3_14_u1c1>;
18 pinctrl-names = "default";
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/ |
| D | adsp_shim.h | 4 * SPDX-License-Identifier: Apache-2.0
19 uint32_t dfspsreq; /* Offset: 0x00 */
21 uint32_t dfspsrsp; /* Offset: 0x10 */
23 uint32_t svcfg; /* Offset: 0x18 */
24 uint32_t dfltrc; /* Offset: 0x1c */
37 uint32_t dfpmccap; /* Offset: 0x00 */
40 uint32_t dfhrosccf; /* Offset: 0x04 */
43 uint32_t dfxosccf; /* Offset: 0x08 */
46 uint32_t dflrosccf; /* Offset: 0x0c */
49 uint32_t dfsiorosccf; /* Offset: 0x10 */
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| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/dma/ |
| D | stm32_dma.h | 4 * SPDX-License-Identifier: Apache-2.0
10 * @name custom DMA flags for channel configuration
13 /** DMA cyclic mode config on bit 5*/
18 /** DMA transfer direction config on bits 6-7 */
25 /** DMA Peripheral increment Address config on bit 9 */
30 /** DMA Memory increment Address config on bit 10 */
35 /** DMA Peripheral data size config on bits 11, 12 */
41 /** DMA Memory data size config on bits 13, 14 */
47 /** DMA Peripheral increment offset config on bit 15 */
50 /** DMA Priority config on bits 16, 17*/
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/dma/ |
| D | dma_stm32.h | 4 * SPDX-License-Identifier: Apache-2.0
10 /* @brief linked_channel value to inform zephyr dma driver that
11 * DMA channel will be handled by HAL
15 /* @brief gives the first DMA channel : 0 or 1 in the register map
16 * when counting channels from 1 to N or from 0 to N-1
19 /* from DTS the dma stream id is in range 0..N-1 */
22 /* from DTS the dma stream id is in range 1..N */
26 /* typically on the stm32H7 serie, DMA V1 with mux */
29 /* from DTS the dma stream id is in range 0..N-1 */
33 /* macro for dma slot (only for dma-v1 or dma-v2 types) */
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| /Zephyr-Core-3.5.0/dts/xtensa/intel/ |
| D | intel_adsp_cavs15.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx4";
19 i-cache-line-size = <64>;
20 d-cache-line-size = <64>;
25 compatible = "cdns,tensilica-xtensa-lx4";
31 compatible = "mmio-sram";
36 compatible = "mmio-sram";
40 sysclk: system-clock {
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| /Zephyr-Core-3.5.0/drivers/pcie/endpoint/ |
| D | pcie_ep_iproc.c | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/drivers/dma.h>
19 static int iproc_pcie_conf_read(const struct device *dev, uint32_t offset, in iproc_pcie_conf_read() argument
22 const struct iproc_pcie_ep_config *cfg = dev->config; in iproc_pcie_conf_read()
24 /* Write offset to Configuration Indirect Address register */ in iproc_pcie_conf_read()
25 pcie_write32(offset, &cfg->base->paxb_config_ind_addr); in iproc_pcie_conf_read()
28 *data = pcie_read32(&cfg->base->paxb_config_ind_data); in iproc_pcie_conf_read()
33 static void iproc_pcie_conf_write(const struct device *dev, uint32_t offset, in iproc_pcie_conf_write() argument
36 const struct iproc_pcie_ep_config *cfg = dev->config; in iproc_pcie_conf_write()
38 /* Write offset to Configuration Indirect Address register */ in iproc_pcie_conf_write()
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| /Zephyr-Core-3.5.0/dts/arm/st/g0/ |
| D | stm32g0b0.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32g0b0", "st,stm32g0", "simple-bus";
13 pinctrl: pin-controller@50000000 {
15 compatible = "st,stm32-gpio";
16 gpio-controller;
17 #gpio-cells = <2>;
24 compatible = "st,stm32-usart", "st,stm32-uart";
33 compatible = "st,stm32-usart", "st,stm32-uart";
42 compatible = "st,stm32-timers";
47 interrupt-names = "global";
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| /Zephyr-Core-3.5.0/drivers/serial/ |
| D | uart_mcux_flexcomm.c | 2 * Copyright (c) 2017, 2022-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
23 #include <zephyr/drivers/dma.h>
71 size_t offset; member
93 const struct mcux_flexcomm_config *config = dev->config; in mcux_flexcomm_poll_in()
94 uint32_t flags = USART_GetStatusFlags(config->base); in mcux_flexcomm_poll_in()
95 int ret = -1; in mcux_flexcomm_poll_in()
98 *c = USART_ReadByte(config->base); in mcux_flexcomm_poll_in()
108 const struct mcux_flexcomm_config *config = dev->config; in mcux_flexcomm_poll_out()
111 while (!(USART_GetStatusFlags(config->base) & kUSART_TxFifoEmptyFlag)) { in mcux_flexcomm_poll_out()
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