Searched full:divn_clk (Results 1 – 5 of 5) sorted by relevance
8 clock-src = <&divn_clk>;20 clock-src = <&divn_clk>;
18 Timer uses divn_clk or lp_clk
85 divn_clk: divn_clk { label245 clock-src = <&divn_clk>;263 clock-src = <&divn_clk>;
28 #define DIVN_CLK 32000000 /* DIVN clock: fixed @32MHz */ macro29 #define SCLK_FREQ_2MHZ (DIVN_CLK / 14) /* 2.285714 MHz*/30 #define SCLK_FREQ_4MHZ (DIVN_CLK / 8) /* 4 MHz */31 #define SCLK_FREQ_8MHZ (DIVN_CLK / 4) /* 8 MHz */32 #define SCLK_FREQ_16MHZ (DIVN_CLK / 2) /* 16 MHz */
341 data->freq = DT_PROP(DT_NODELABEL(divn_clk), clock_frequency) / in counter_smartbond_init_timer()522 DT_NODELABEL(divn_clk)) ? 1 : 0, \
