| /Zephyr-Core-3.6.0/dts/bindings/pwm/ |
| D | raspberrypi,pico-pwm.yaml | 17 divider-int-0:
21 The integral part of the divider for pwm slice 0.
25 divider-frac-0:
29 The fractional part of the divider for pwm slice 0.
33 divider-int-1:
36 description: See divider-int-0 for help
38 divider-frac-1:
41 description: See divider-frac-0 for help
43 divider-int-2:
46 description: See divider-int-0 for help
[all …]
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| /Zephyr-Core-3.6.0/tests/drivers/sensor/adltc2990/boards/ |
| D | native_sim.overlay | 13 pin-v1-voltage-divider-resistors = <500 1000>;
14 pin-v2-voltage-divider-resistors = <110000 100000>;
15 pin-v3-voltage-divider-resistors = <7000 1000>;
16 pin-v4-voltage-divider-resistors = <500 1000>;
27 pin-v1-voltage-divider-resistors = <0 1>;
28 pin-v2-voltage-divider-resistors = <0 1>;
29 pin-v3-voltage-divider-resistors = <0 1>;
30 pin-v4-voltage-divider-resistors = <0 1>;
39 pin-v1-voltage-divider-resistors = <0 1>;
40 pin-v2-voltage-divider-resistors = <0 1>;
[all …]
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| /Zephyr-Core-3.6.0/dts/bindings/iio/afe/ |
| D | voltage-divider.yaml | 5 Description for a voltage divider, with optional ability to measure
8 compatible: "voltage-divider"
16 Channels available with this divider configuration.
22 Resistance of the lower leg of the voltage divider
27 Resistance of the full path through the voltage divider.
35 Control power to the voltage divider inputs.
38 to enable the divider input.
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| /Zephyr-Core-3.6.0/soc/arm/nxp_imx/rt/ |
| D | flexspi_rt11xx.c | 21 uint32_t divider; in flexspi_clock_set_freq() local
41 /* Select a divider based on root clock frequency. We round the in flexspi_clock_set_freq()
42 * divider up, so that the resulting clock frequency is lower than in flexspi_clock_set_freq()
45 divider = ((root_rate + (rate - 1)) / rate); in flexspi_clock_set_freq()
46 /* Cap divider to max value */ in flexspi_clock_set_freq()
47 divider = MIN(divider, CCM_CLOCK_ROOT_CONTROL_DIV_MASK); in flexspi_clock_set_freq()
56 CLOCK_SetRootClockDiv(flexspi_clk, divider); in flexspi_clock_set_freq()
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| D | flexspi_rt10xx.c | 16 uint8_t divider; in flexspi_clock_set_freq() local
44 /* Select a divider based on root frequency. in flexspi_clock_set_freq()
45 * if we can't get an exact divider, round down in flexspi_clock_set_freq()
47 divider = ((root_rate + (rate - 1)) / rate) - 1; in flexspi_clock_set_freq()
48 /* Cap divider to max value */ in flexspi_clock_set_freq()
49 divider = MIN(divider, kCLOCK_FlexspiDivBy8); in flexspi_clock_set_freq()
58 CLOCK_SetDiv(div_sel, divider); in flexspi_clock_set_freq()
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| /Zephyr-Core-3.6.0/dts/bindings/i3c/ |
| D | nxp,mcux-i3c.yaml | 25 clk-divider:
27 description: Main clock divider for I3C
30 clk-divider-tc:
32 description: TC clock divider for I3C
35 clk-divider-slow:
37 description: Slow clock divider for I3C
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| /Zephyr-Core-3.6.0/drivers/mdio/ |
| D | mdio_xmc4xxx.c | 30 uint8_t divider; member
35 {.divider = 8, .reg_val = 2}, {.divider = 13, .reg_val = 3},
36 {.divider = 21, .reg_val = 0}, {.divider = 31, .reg_val = 1},
37 {.divider = 51, .reg_val = 4}, {.divider = 62, .reg_val = 5},
125 uint8_t divider = mdio_clock_divider[i].divider; in mdio_xmc4xxx_set_clock_divider() local
127 uint32_t mdc_clk = eth_mac_clk / divider; in mdio_xmc4xxx_set_clock_divider()
130 LOG_DBG("Using MDC clock divider %d", divider); in mdio_xmc4xxx_set_clock_divider()
157 LOG_ERR("Error setting MDIO clock divider"); in mdio_xmc4xxx_initialize()
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| /Zephyr-Core-3.6.0/drivers/pwm/ |
| D | pwm_sam.c | 30 uint8_t divider; member
38 uint8_t divider = config->divider; in sam_pwm_get_cycles_per_sec() local
41 ((1 << prescaler) * divider); in sam_pwm_get_cycles_per_sec()
101 uint8_t divider = config->divider; in sam_pwm_init() local
104 /* FIXME: way to validate prescaler & divider */ in sam_pwm_init()
116 pwm->PWM_CLK = PWM_CLK_PREA(prescaler) | PWM_CLK_DIVA(divider); in sam_pwm_init()
133 .divider = DT_INST_PROP(inst, divider), \
|
| /Zephyr-Core-3.6.0/dts/bindings/clock/ |
| D | litex,clk.yaml | 52 minimal global divider
57 maximal global divider
72 minimal frequency after global divider and multiplier
77 maximal frequency after global divider and multiplier
82 minimal clock output divider
87 maximal clock output divider
|
| D | raspberrypi,pico-pll.yaml | 16 The feedback divider value.
23 The post clock divider.
30 The post clock divider.
|
| /Zephyr-Core-3.6.0/soc/arm/nxp_kinetis/k8x/ |
| D | Kconfig.soc | 45 int "Freescale K8x core clock divider"
52 int "Freescale K8x bus clock divider"
59 int "Freescale K8x FlexBus clock divider"
66 int "Freescale K8x flash clock divider"
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| /Zephyr-Core-3.6.0/samples/boards/nrf/battery/ |
| D | README.rst | 14 ``voltage-divider`` then the voltage is measured using that divider. An
15 example of a devicetree node describing a voltage divider for battery
22 compatible = "voltage-divider";
30 * If the board does not have a voltage divider and so no ``/vbatt`` node
45 Note that in many cases where there is no voltage divider the digital
66 A Nordic-based board, optionally with a voltage divider specified in its
|
| /Zephyr-Core-3.6.0/drivers/clock_control/ |
| D | clock_control_lpc11u6x.h | 79 volatile uint32_t sys_ahb_clk_div; /* System clock divider */
83 volatile uint32_t ssp0_clk_div; /* SSP0 clock divider */
84 volatile uint32_t usart0_clk_div; /* USART0 clock divider */
85 volatile uint32_t ssp1_clk_div; /* SSP1 clock divider */
87 * rate generator clock divider
92 volatile uint32_t usb_clk_div; /* USB clock divider */
96 volatile uint32_t clk_out_div; /* CLKOUT divider */
99 * generator divider
110 volatile uint32_t iocon_clk_div[7]; /* IOCON clock divider */
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| D | clock_control_r8a7795_cpg_mssr.c | 194 /* according to documentation, divider value stored in reg is equal to: val + 1 */ in r8a7795_get_div_helper()
204 static int r8a7795_set_rate_helper(uint32_t module, uint32_t *divider, uint32_t *div_mask) in r8a7795_set_rate_helper() argument
212 if (*divider == 2 || *divider == 4) { in r8a7795_set_rate_helper()
214 *divider >>= 2; in r8a7795_set_rate_helper()
224 /* divider should be power of two and max possible value 16 */ in r8a7795_set_rate_helper()
225 if (!is_power_of_two(*divider) || *divider > 16) { in r8a7795_set_rate_helper()
230 *divider = (find_lsb_set(*divider) - 1) << R8A7795_CLK_SDH_DIV_SHIFT; in r8a7795_set_rate_helper()
234 /* according to documentation, divider value stored in reg is equal to: val + 1 */ in r8a7795_set_rate_helper()
235 *divider -= 1; in r8a7795_set_rate_helper()
236 if (*divider <= R8A7795_CLK_CANFD_DIV_MASK) { in r8a7795_set_rate_helper()
|
| D | clock_control_renesas_cpg_mssr.c | 94 uint32_t divider = RCAR_CPG_NONE; in rcar_cpg_get_divider() local
111 divider = data->get_div_helper(reg_val, clk_info->module); in rcar_cpg_get_divider()
114 if (!divider) { in rcar_cpg_get_divider()
118 return divider; in rcar_cpg_get_divider()
123 uint32_t divider = rcar_cpg_get_divider(dev, clk_info); in rcar_cpg_update_out_freq() local
125 if (divider == RCAR_CPG_NONE) { in rcar_cpg_update_out_freq()
129 clk_info->out_freq = clk_info->in_freq / divider; in rcar_cpg_update_out_freq()
196 * - divider is zero (with current implementation of board specific in rcar_cpg_change_children_in_out_freq()
197 * divider helper function it is impossible); in rcar_cpg_change_children_in_out_freq()
198 * - we don't have board specific implementation of get divider helper in rcar_cpg_change_children_in_out_freq()
[all …]
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| /Zephyr-Core-3.6.0/samples/sensor/lps22hh_i3c/boards/ |
| D | mimxrt685_evk_cm33.overlay | 14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
|
| /Zephyr-Core-3.6.0/samples/sensor/lsm6dso_i2c_on_i3c/boards/ |
| D | mimxrt685_evk_cm33.overlay | 14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
|
| /Zephyr-Core-3.6.0/soc/arm/nxp_imx/rt5xx/ |
| D | flash_clock_setup.c | 75 * flexspi_set_clock run in RAM used to configure FlexSPI clock source and divider
78 void flexspi_setup_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider) in flexspi_setup_clock() argument
83 (divider - 1))) { in flexspi_setup_clock()
95 /* Reset the divider counter */ in flexspi_setup_clock()
97 CLKCTL0->FLEXSPI0FCLKDIV = CLKCTL0_FLEXSPI0FCLKDIV_DIV(divider - 1); in flexspi_setup_clock()
108 (divider - 1))) { in flexspi_setup_clock()
120 /* Reset the divider counter */ in flexspi_setup_clock()
122 CLKCTL0->FLEXSPI1FCLKDIV = CLKCTL0_FLEXSPI1FCLKDIV_DIV(divider - 1); in flexspi_setup_clock()
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| D | soc.c | 48 /* Numerator of the SYSPLL0 fractional loop divider is 0 */
50 /* Denominator of the SYSPLL0 fractional loop divider is 1 */
59 /* Numerator of the Audio PLL fractional loop divider is 0 */
61 /* Denominator of the Audio PLL fractional loop divider is 1 */
70 .divider = 255U,
77 .divider = 255U,
244 /* Let CPU run on FRO with divider 2 for safe switching. */ in rt5xx_clock_init()
270 /* Set SYSCPUAHBCLKDIV divider to value 2 */ in rt5xx_clock_init()
309 /* Attach main clock to I3C, divider will be set in i3c_mcux.c */ in rt5xx_clock_init()
331 * this means the clock divider will vary depending on in rt5xx_clock_init()
[all …]
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| /Zephyr-Core-3.6.0/soc/arm/nxp_kinetis/ke1xf/ |
| D | soc.c | 36 "Invalid SCG slow clock divider value");
38 "Invalid SCG bus clock divider value");
40 /* Core divider range is 1 to 4 with SPLL as clock source */
42 "Invalid SCG core clock divider value");
45 "Invalid SCG core clock divider value");
67 "Invalid SCG SOSC divider 1 value");
69 "Invalid SCG SOSC divider 2 value");
82 "Invalid SCG SIRC divider 1 value");
84 "Invalid SCG SIRC divider 2 value");
100 "Invalid SCG FIRC divider 1 value");
[all …]
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| /Zephyr-Core-3.6.0/samples/basic/blinky_pwm/boards/ |
| D | rpi_pico.overlay | 7 divider-frac-4 = <15>;
8 divider-int-4 = <255>;
|
| /Zephyr-Core-3.6.0/tests/boards/intel_adsp/ssp/ |
| D | Kconfig | 12 bool "Use mn divider"
14 Use MN divider.
|
| /Zephyr-Core-3.6.0/soc/riscv/sifive_freedom/u700/ |
| D | clock.c | 37 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in fu740_clock_init()
39 PLL_Q(2) | /* output divider: VCO / 2^2 = 1001MHz */ in fu740_clock_init()
51 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in fu740_clock_init()
53 PLL_Q(4) | /* output divider: VCO / 2^4 = 250.25MHz */ in fu740_clock_init()
65 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in fu740_clock_init()
67 PLL_Q(2) | /* output divider: VCO / 2^2 = 936MHz */ in fu740_clock_init()
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| /Zephyr-Core-3.6.0/samples/drivers/led_pwm/boards/ |
| D | rpi_pico.overlay | 13 divider-frac-4 = <15>;
14 divider-int-4 = <255>;
|
| /Zephyr-Core-3.6.0/dts/bindings/watchdog/ |
| D | nxp,lpc-wwdt.yaml | 17 clk-divider:
19 description: Watchdog clock divider
|
