| /Zephyr-Core-3.5.0/scripts/kconfig/ |
| D | kconfigfunctions.py | 202 The function will divide the value based on 'unit':
204 'k' or 'K' divide by 1024 (1 << 10)
205 'm' or 'M' divide by 1,048,576 (1 << 20)
206 'g' or 'G' divide by 1,073,741,824 (1 << 30)
207 'kb' or 'Kb' divide by 8192 (1 << 13)
208 'mb' or 'Mb' divide by 8,388,608 (1 << 23)
209 'gb' or 'Gb' divide by 8,589,934,592 (1 << 33)
231 The function will divide the value based on 'unit':
233 'k' or 'K' divide by 1024 (1 << 10)
234 'm' or 'M' divide by 1,048,576 (1 << 20)
[all …]
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| /Zephyr-Core-3.5.0/drivers/adc/ |
| D | Kconfig.mcux | 47 prompt "Clock Divide Selection"
51 bool "Divide ratio is 1"
54 bool "Divide ratio is 2"
57 bool "Divide ratio is 4"
60 bool "Divide ratio is 8"
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| /Zephyr-Core-3.5.0/soc/arm/nxp_kinetis/k8x/ |
| D | Kconfig.soc | 48 This option specifies the divide value for the K8x processor core clock
55 This option specifies the divide value for the K8x bus clock from the
62 This option specifies the divide value for the K8x FlexBus clock from the
69 This option specifies the divide value for the K8x flash clock from the
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| D | soc.c | 67 /* Divide PLL output frequency by 2 for peripherals */
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| /Zephyr-Core-3.5.0/dts/bindings/clock/ |
| D | litex,clk.yaml | 48 litex,divclk-divide-min:
53 litex,divclk-divide-max:
78 litex,clkout-divide-min:
83 litex,clkout-divide-max:
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| D | microchip,xec-pcr.yaml | 17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
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| /Zephyr-Core-3.5.0/cmake/compiler/gcc/ |
| D | target_x86.cmake | 21 # In order to use division, `--divide` needs to be passed to
23 list(APPEND TOOLCHAIN_C_FLAGS -Wa,--divide)
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| /Zephyr-Core-3.5.0/soc/arm/nxp_kinetis/ |
| D | Kconfig | 74 Selects the amount to divide down the external reference clock for the PLL.
82 Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
91 Selects the amount to divide down the fast internal reference clock. The
99 Selects the amount to divide down the external reference clock for the
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| /Zephyr-Core-3.5.0/tests/arch/x86/static_idt/src/ |
| D | main.c | 75 * This is the handler for the divide by zero exception.
77 * The source of this divide-by-zero error comes from the following line in
88 * loop of divide-by-zero errors would be created.)
159 volatile int error; /* used to create a divide by zero error */ in ZTEST()
175 * issuing a 'divide by zero' warning. in ZTEST()
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| /Zephyr-Core-3.5.0/dts/bindings/sensor/ |
| D | ti,fdc2x1x.yaml | 233 1 = divide by 1. Choose for sensor frequencies between
235 2 = divide by 2. Choose for sensor frequencies between 5MHz
239 2 = divide by 2. Choose for sensor frequencies between
242 - 1 # Divide by 1
243 - 2 # Divide by 2
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| /Zephyr-Core-3.5.0/tests/ztest/error_hook/src/ |
| D | main.c | 97 * Do not optimize the divide instruction. GCC will generate invalid
98 * opcode exception instruction instead of real divide instruction.
105 /* divide by zero */ in trigger_fault_divide_zero()
112 * trigger an exception for divide zero. They might need to enable the divide in trigger_fault_divide_zero()
116 * which does not include a divide instruction, the test is skipped, in trigger_fault_divide_zero()
118 * For ARMv8-R, divide by zero trapping is not supported in hardware. in trigger_fault_divide_zero()
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| /Zephyr-Core-3.5.0/dts/bindings/timer/ |
| D | nxp,s32-sys-timer.yaml | 24 Selects the module clock divide value for the prescaler, between 1 and 256.
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| /Zephyr-Core-3.5.0/soc/arm/atmel_sam/sam4l/ |
| D | soc.c | 90 static inline uint32_t pll_config_init(uint32_t divide, uint32_t mul) in pll_config_init() argument
98 /* Divide output frequency by two */ in pll_config_init()
115 vco_hz /= divide; in pll_config_init()
134 (divide << SCIF_PLL_PLLDIV_Pos) | in pll_config_init()
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| /Zephyr-Core-3.5.0/dts/bindings/can/ |
| D | st,stm32-fdcan.yaml | 41 Divide by 1 is the peripherals reset value and remains set unless
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| D | microchip,mcp251xfd.yaml | 74 description: The factor to divide the system clock for CLKO pin.
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| /Zephyr-Core-3.5.0/subsys/shell/ |
| D | shell_help.c | 13 * It takes care to not divide words.
65 * divide in the way to not divide words. in formatted_text_print()
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| /Zephyr-Core-3.5.0/dts/riscv/ |
| D | riscv32-litex-vexriscv.dtsi | 311 litex,divclk-divide-min = <1>;
312 litex,divclk-divide-max = <107>;
317 litex,clkout-divide-min = <1>;
318 litex,clkout-divide-max = <126>;
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| /Zephyr-Core-3.5.0/arch/x86/core/ |
| D | ia32.cmake | 9 zephyr_compile_options($<$<COMPILE_LANGUAGE:ASM>:-Wa,--divide>)
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| /Zephyr-Core-3.5.0/dts/bindings/serial/ |
| D | cdns,uart.yaml | 24 description: Baud Rate Divide register value.
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| /Zephyr-Core-3.5.0/dts/bindings/pwm/ |
| D | infineon,xmc4xxx-ccu8-pwm.yaml | 24 a separate prescaler to divide the clock. The clock divider is
95 The entry in the array will divide CCU clock by (2 << value).
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| D | infineon,xmc4xxx-ccu4-pwm.yaml | 74 The entry in the array will divide CCU clock by (2 << value).
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| /Zephyr-Core-3.5.0/drivers/sensor/vl53l1x/ |
| D | vl53l1_platform_user_config.h | 52 * FW stream divide - value of 254
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| /Zephyr-Core-3.5.0/dts/bindings/display/ |
| D | ftdi,ft800.yaml | 19 The value to divide the main clock by for PCLK. If the
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| /Zephyr-Core-3.5.0/arch/riscv/ |
| D | Kconfig.isa | 31 which is named "M" and contains instructions that multiply or divide
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| /Zephyr-Core-3.5.0/arch/xtensa/core/ |
| D | fatal.c | 53 return "divide by zero"; in z_xtensa_exccause()
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