Searched full:div2 (Results 1 – 18 of 18) sorted by relevance
| /Zephyr-Core-3.7.0/dts/bindings/dac/ |
| D | ti,dacx0501.yaml | 26 - "div2"
29 resolution. mul2 will double the output range but lower the resolution, while div2 will
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| /Zephyr-Core-3.7.0/dts/bindings/clock/ |
| D | st,stm32wba-hse-clock.yaml | 11 hse-div2:
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| D | st,stm32wl-hse-clock.yaml | 17 hse-div2:
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| D | raspberrypi,pico-pll.yaml | 26 post-div2:
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| /Zephyr-Core-3.7.0/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/ |
| D | hse_16.overlay | 14 hse-div2;
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| /Zephyr-Core-3.7.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/ |
| D | wl_pll_48_hse_32.overlay | 15 hse-div2;
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| D | clear_clocks.overlay | 17 /delete-property/ hse-div2;
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| /Zephyr-Core-3.7.0/soc/openisa/rv32m1/ |
| D | soc.c | 35 .div2 = kSCG_AsyncClkDivBy1,
58 .div2 = kSCG_AsyncClkDisable,
180 .div2 = kSCG_AsyncClkDivBy2, in rv32m1_switch_to_sirc()
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| /Zephyr-Core-3.7.0/soc/nxp/kinetis/ke1xf/ |
| D | soc.c | 75 .div2 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(soscdiv2_clk)),
88 .div2 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(sircdiv2_clk)),
106 .div2 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(fircdiv2_clk)),
136 .div2 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(splldiv2_clk)),
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| /Zephyr-Core-3.7.0/soc/nxp/kinetis/ke1xz/ |
| D | soc.c | 54 .div2 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(sircdiv2_clk)),
69 .div2 = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(fircdiv2_clk)), /* b20253 */
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| /Zephyr-Core-3.7.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
| D | wb_i2c1_sysclk_lptim1_lsi.overlay | 16 /delete-property/ hse-div2;
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| D | wb_i2c1_hsi_lptim1_lse.overlay | 16 /delete-property/ hse-div2;
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| D | wl_i2c1_sysclk_lptim1_lsi.overlay | 16 /delete-property/ hse-div2;
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| D | wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay | 16 /delete-property/ hse-div2;
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| /Zephyr-Core-3.7.0/boards/st/nucleo_wba55cg/ |
| D | nucleo_wba55cg.dts | 87 hse-div2;
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| /Zephyr-Core-3.7.0/dts/arm/rpi_pico/ |
| D | rp2040.dtsi | 126 post-div2 = <2>;
137 post-div2 = <5>;
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| /Zephyr-Core-3.7.0/soc/nxp/imx/imx7d/ |
| D | soc.c | 35 /* We need system PLL Div2 to run M4 core */ in SOC_ClockInit()
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| /Zephyr-Core-3.7.0/drivers/clock_control/ |
| D | clock_control_rpi_pico.c | 723 "pll_sys: post-div2 is out of range");
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