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/Zephyr-latest/dts/bindings/ethernet/
Dxlnx,gem.yaml3 # SPDX-License-Identifier: Apache-2.0
10 include: ethernet-controller.yaml
19 clock-frequency:
27 which it will be adjusted at run-time. Therefore, the value of this
29 respective GEM's TX clock - by default, this is the IO PLL.
31 mdc-divider:
42 init-mdio-phy:
45 Activates the management of a PHY associated with the controller in-
46 stance. If this parameter is activated at the board level, the de-
47 fault values of the associated parameters mdio-phy-address, phy-poll-
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/Zephyr-latest/dts/arm/xilinx/
Dzynqmp.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-r.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
16 compatible = "xlnx,pinctrl-zynqmp";
19 compatible = "soc-nv-flash";
24 compatible = "mmio-sram";
29 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
31 zephyr,memory-region = "OCM";
40 interrupt-names = "irq_0";
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Dzynq7000.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-a.dtsi>
8 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
9 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
13 interrupt-parent = <&gic>;
16 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
18 zephyr,memory-region = "OCM_LOW";
22 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
24 zephyr,memory-region = "OCM_HIGH";
28 compatible = "arm,armv8-timer";
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/Zephyr-latest/drivers/ethernet/
Deth_stellaris.c5 * SPDX-License-Identifier: Apache-2.0
43 struct eth_stellaris_runtime *dev_data = dev->data; in eth_stellaris_flush()
45 if (dev_data->tx_pos != 0) { in eth_stellaris_flush()
46 sys_write32(dev_data->tx_word, REG_MACDATA); in eth_stellaris_flush()
47 dev_data->tx_pos = 0; in eth_stellaris_flush()
48 dev_data->tx_word = 0U; in eth_stellaris_flush()
54 struct eth_stellaris_runtime *dev_data = dev->data; in eth_stellaris_send_byte()
56 dev_data->tx_word |= byte << (dev_data->tx_pos * 8); in eth_stellaris_send_byte()
57 dev_data->tx_pos++; in eth_stellaris_send_byte()
58 if (dev_data->tx_pos == 4) { in eth_stellaris_send_byte()
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Deth_xlnx_gem_priv.h7 * SPDX-License-Identifier: Apache-2.0
22 #define ETH_XLNX_BUFFER_ALIGNMENT 4 /* RX/TX buffer alignment (in bytes) */
26 /* Receive Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-2. */
30 * [31 .. 02] Mask for effective buffer address -> excludes [1..0]
31 * [01] Wrap bit, last BD in RX BD ring
45 * [24] this bit has different semantics depending on whether RX checksum
47 * [23 .. 22] These bits have different semantics depending on whether RX check-
54 * [15] End-of-frame bit
55 * [14] Start-of-frame bit
56 * [13] FCS status bit for FCS ignore mode
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Deth_smsc911x.c2 * Copyright (c) 2017-2018 ARM Limited
5 * SPDX-License-Identifier: Apache-2.0
61 SMSC9220->MAC_CSR_CMD = cmd; in smsc_mac_regread()
63 while ((SMSC9220->MAC_CSR_CMD & MAC_CSR_CMD_BUSY) != 0) { in smsc_mac_regread()
66 *val = SMSC9220->MAC_CSR_DATA; in smsc_mac_regread()
75 SMSC9220->MAC_CSR_DATA = val; in smsc_mac_regwrite()
77 SMSC9220->MAC_CSR_CMD = cmd; in smsc_mac_regwrite()
79 while ((SMSC9220->MAC_CSR_CMD & MAC_CSR_CMD_BUSY) != 0) { in smsc_mac_regwrite()
92 return -1; in smsc_phy_regread()
97 return -EBUSY; in smsc_phy_regread()
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Deth_xlnx_gem.c5 * SPDX-License-Identifier: Apache-2.0
8 * - Only supports 32-bit addresses in buffer descriptors, therefore
9 * the ZynqMP APU (Cortex-A53 cores) may not be fully supported.
10 * - Hardware timestamps not considered.
11 * - VLAN tags not considered.
12 * - Wake-on-LAN interrupt not supported.
13 * - Send function is not SMP-capable (due to single TX done semaphore).
14 * - Interrupt-driven PHY management not supported - polling only.
15 * - No explicit placement of the DMA memory area(s) in either a
18 * with the Cortex-R5 QEMU target or an actual R5 running without the
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/Zephyr-latest/subsys/canbus/isotp/
DKconfig1 # ISO-TP configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 bool "ISO-TP Transport [EXPERIMENTAL]"
18 module-str = ISOTP
34 Timeout for the reception of the next FC frame. ISO 15765-2: 1000ms
42 ISO 15765-2: 1000ms
50 ISO 15765-2: 1000ms
55 If enabled, SFs, FCs and the last CF must always have a DLC of 8 bytes
83 CAN_MAX_DLEN - 1 (for classic CAN : 8 - 1 = 7, for CAN FD : 64 - 1 = 63).
92 Each buffer will occupy CAN_MAX_DLEN - 1 byte + header (sizeof(struct net_buf))
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/Zephyr-latest/samples/net/wpan_serial/src/
Dmain.c2 * Copyright (c) 2016-2019 Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief App implementing 802.15.4 "serial-radio" protocol
11 * Application implementing 802.15.4 "serial-radio" protocol compatible
12 * with popular Contiki-based native border routers.
28 #define THREAD_PRIORITY K_PRIO_COOP(CONFIG_NUM_COOP_PRIORITIES - 1)
44 /* RX queue */
85 LOG_DBG("garbage: discard byte %x", c); in slip_process_byte()
124 buf = net_buf_frag_last(pkt_curr->buffer); in slip_process_byte()
126 LOG_ERR("No more buf space: buf %p len %u", buf, buf->len); in slip_process_byte()
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