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/Zephyr-Core-3.5.0/dts/bindings/serial/
Dnordic,nrf-uart-common.yaml1 include: [uart-controller.yaml, pinctrl-device.yaml]
10 pinctrl-0:
13 disable-rx:
16 Disable UART reception capabilities (only required to disable reception
19 current-speed:
24 - 1200
25 - 2400
26 - 4800
27 - 9600
28 - 14400
[all …]
/Zephyr-Core-3.5.0/soc/arm/nuvoton_npcx/common/
Dsoc_power.h4 * SPDX-License-Identifier: Apache-2.0
15 * @brief Disable UART RX wake-up interrupt.
20 * @brief Enable UART RX wake-up interrupt.
/Zephyr-Core-3.5.0/drivers/net/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
13 bool "Point-to-point (PPP) UART based driver"
50 PPP ring buffer size when passing data from RX ISR to worker
57 Sets the stack size which will be used by the PPP RX workqueue.
60 int "RX workqueue thread priority"
63 Sets the priority of the RX workqueue thread.
70 to disable this as it takes some time to verify the received
77 six hex 8-bit chars separated by colons (e.g.:
89 bool "Disable PPP interface auto-start"
91 This option allows user to disable autostarting of the PPP interface
[all …]
/Zephyr-Core-3.5.0/tests/drivers/uart/uart_pm/
Dnrf_rx_disable.overlay1 /* SPDX-License-Identifier: Apache-2.0 */
4 disable-rx;
/Zephyr-Core-3.5.0/dts/bindings/ethernet/
Dxlnx,gem.yaml3 # SPDX-License-Identifier: Apache-2.0
10 include: ethernet-controller.yaml
19 clock-frequency:
27 which it will be adjusted at run-time. Therefore, the value of this
29 respective GEM's TX clock - by default, this is the IO PLL.
31 mdc-divider:
42 init-mdio-phy:
45 Activates the management of a PHY associated with the controller in-
46 stance. If this parameter is activated at the board level, the de-
47 fault values of the associated parameters mdio-phy-address, phy-poll-
[all …]
/Zephyr-Core-3.5.0/samples/drivers/spi_flash_at45/boards/
Dnrf9160dk_nrf9160.overlay4 * SPDX-License-Identifier: Apache-2.0
21 low-power-enable;
27 pinctrl-0 = <&spi3_default_alt>;
28 pinctrl-1 = <&spi3_sleep_alt>;
29 pinctrl-names = "default", "sleep";
30 cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>,
36 spi-max-frequency = <15000000>;
37 jedec-id = [1f 24 00];
39 sector-size = <65536>;
40 block-size = <2048>;
[all …]
/Zephyr-Core-3.5.0/drivers/ethernet/
Deth_smsc91x_priv.h3 * SPDX-License-Identifier: Apache-2.0
19 #define TCR_TXENA 0x0001 /* Enable/disable transmitter */
29 #define RCR_RXEN 0x0100 /* Enable/disable receiver */
30 #define RCR_STRIP_CRC 0x0200 /* Strip CRC from RX packets */
48 #define RPCR_DPLX 0x1000 /* Put PHY in full-duplex mode */
54 #define RPCR_LED_LINK_FDX 0x3 /* Full-duplex link detect */
56 #define RPCR_LED_ACT_ANY 0x4 /* TX or RX activity detected */
57 #define RPCR_LED_ACT_RX 0x6 /* RX activity detected */
62 #define CR_EPH_POWER_EN 0x8000 /* Disable/enable low power mode */
86 #define MMUCR_CMD_RELEASE 4 /* Remove and release from RX FIFO */
[all …]
Deth_xlnx_gem_priv.h7 * SPDX-License-Identifier: Apache-2.0
22 #define ETH_XLNX_BUFFER_ALIGNMENT 4 /* RX/TX buffer alignment (in bytes) */
26 /* Receive Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-2. */
30 * [31 .. 02] Mask for effective buffer address -> excludes [1..0]
31 * [01] Wrap bit, last BD in RX BD ring
45 * [24] this bit has different semantics depending on whether RX checksum
47 * [23 .. 22] These bits have different semantics depending on whether RX check-
54 * [15] End-of-frame bit
55 * [14] Start-of-frame bit
78 /* Transmit Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-3. */
[all …]
/Zephyr-Core-3.5.0/samples/bluetooth/direction_finding_central/
Doverlay-aod.conf4 # SPDX-License-Identifier: Apache-2.0
7 # Disable AoA Feature (antenna switching) in Rx mode in Controller and Host
/Zephyr-Core-3.5.0/samples/bluetooth/direction_finding_connectionless_rx/
Doverlay-aod.conf4 # SPDX-License-Identifier: Apache-2.0
7 # Disable AoA Feature (antenna switching) in Rx mode in Controller and Host
/Zephyr-Core-3.5.0/dts/bindings/spi/
Dnxp,imx-flexspi.yaml1 # Copyright 2018-2023, NXP
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,imx-flexspi"
8 include: [spi-controller.yaml, pinctrl-device.yaml]
17 ahb-bufferable:
23 ahb-cacheable:
29 ahb-prefetch:
34 ahb-read-addr-opt:
40 combination-mode:
46 sck-differential-clock:
[all …]
/Zephyr-Core-3.5.0/subsys/lorawan/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
20 module-str = lorawan
24 int "LoRaWAN System Max Rx Error"
27 System Max Rx timing error value in ms to be used by LoRaWAN stack
35 Disable for private LoRaWAN networks.
/Zephyr-Core-3.5.0/drivers/serial/
Duart_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
50 /* Disable interrupts on UART1 RX pin to avoid repeated interrupts. */ in uart1_wui_isr()
51 (void)gpio_pin_interrupt_configure(gpio, (find_msb_set(pins) - 1), in uart1_wui_isr()
54 /* Refresh console expired time if got UART Rx wake-up event */ in uart1_wui_isr()
63 k_work_reschedule(&uart_console_data->rx_refresh_timeout_work, delay); in uart1_wui_isr()
70 /* Disable interrupts on UART2 RX pin to avoid repeated interrupts. */ in uart2_wui_isr()
71 (void)gpio_pin_interrupt_configure(gpio, (find_msb_set(pins) - 1), in uart2_wui_isr()
74 /* Refresh console expired time if got UART Rx wake-up event */ in uart2_wui_isr()
83 k_work_reschedule(&uart_console_data->rx_refresh_timeout_work, delay); in uart2_wui_isr()
90 const struct uart_it8xxx2_config *const config = dev->config; in uart_it8xxx2_pm_action()
[all …]
Duart_xlnx_ps.c1 /* uart_xlnx_ps.c - Xilinx Zynq family serial driver */
6 * SPDX-License-Identifier: Apache-2.0
19 * - the following macro for the number of bytes between register addresses:
42 * Comp. Xilinx Zynq-7000 Technical Reference Manual (ug585), chap. B.33
49 #define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
53 #define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
54 #define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
62 #define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
67 #define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
70 #define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
[all …]
Duart_mcux_flexcomm.c2 * Copyright (c) 2017, 2022-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
93 const struct mcux_flexcomm_config *config = dev->config; in mcux_flexcomm_poll_in()
94 uint32_t flags = USART_GetStatusFlags(config->base); in mcux_flexcomm_poll_in()
95 int ret = -1; in mcux_flexcomm_poll_in()
98 *c = USART_ReadByte(config->base); in mcux_flexcomm_poll_in()
108 const struct mcux_flexcomm_config *config = dev->config; in mcux_flexcomm_poll_out()
111 while (!(USART_GetStatusFlags(config->base) & kUSART_TxFifoEmptyFlag)) { in mcux_flexcomm_poll_out()
114 USART_WriteByte(config->base, c); in mcux_flexcomm_poll_out()
119 const struct mcux_flexcomm_config *config = dev->config; in mcux_flexcomm_err_check()
[all …]
Duart_cdns.c3 * SPDX-License-Identifier: Apache-2.0
15 ((const struct uart_cdns_device_config *const)(dev)->config)->port)
20 return ((uart_regs->channel_status & CSR_TFUL_MASK) != 0); in uart_cdns_is_tx_fifo_full()
26 return ((uart_regs->channel_status & CSR_TEMPTY_MASK) != 0); in uart_cdns_is_tx_fifo_empty()
29 /** Check if rx FIFO is empty */
32 return ((uart_regs->channel_status & CSR_REMPTY_MASK) != 0); in uart_cdns_is_rx_fifo_empty()
40 uart_regs->baud_rate_div = dev_cfg->bdiv; in uart_cdns_set_baudrate()
51 uart_regs->baud_rate_gen = (dev_cfg->sys_clk_freq + ((dev_cfg->bdiv + 1) * baud_rate) / 2) / in uart_cdns_set_baudrate()
52 ((dev_cfg->bdiv + 1) * baud_rate); in uart_cdns_set_baudrate()
61 uart_regs->rx_tx_fifo = (uint32_t)out_char; in uart_cdns_poll_out()
[all …]
/Zephyr-Core-3.5.0/dts/bindings/pinctrl/
Dti,cc32xx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route UART0 RX to pin 55 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
37 /* configure pin 57 as UART0 RX and pin 62 as UART0 RTS */
39 /* both pin 57 and 62 have pull-up enabled */
40 bias-pull-up;
53 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
56 - drive-push-pull: Push-pull drive mode (default, not required).
[all …]
Draspberrypi,pico-pinctrl.yaml3 # SPDX-License-Identifier: Apache-2.0
7 pin function selection and pin properties, such as routing a UART0 Rx
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
37 /* configure P1 as UART0 RX */
40 input-enable;
54 pins, such as the 'input-enable' property in group 2. Here is a list of
57 - bias-disable: Disable pull-up/down (default, not required).
58 - bias-pull-up: Enable pull-up resistor.
[all …]
/Zephyr-Core-3.5.0/boards/arm/zybo/
Dzybo-pinctrl.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pinctrl/pinctrl-zynq.h>
10 pinctrl_uart1_default: uart1-default {
18 slew-rate = <IO_SPEED_SLOW>;
19 power-source = <IO_STANDARD_LVCMOS18>;
22 conf-rx {
24 bias-high-impedance;
27 conf-tx {
29 bias-disable;
/Zephyr-Core-3.5.0/tests/drivers/uart/uart_basic_api/src/
Dtest_uart_pending.c4 * SPDX-License-Identifier: Apache-2.0
15 * more RX and TX pending interrupts.
19 * RX IRQ is enabled to let received data cause a RX IRQ and so set the
20 * RX IRQ pending flag.
23 * receive serial data, which will trigger a RX IRQ.
25 * Once a RX IRQ happens RX data is read by uart_fifo_read() until there
26 * is no more RX data to be popped from FIFO and all IRQs are handled.
33 * even tho there aren't any further RX and TX IRQs to be processed it
58 * received data until there is no more RX data, thus in uart_pending_callback()
60 * that there are no more RX interrupts to be processed. in uart_pending_callback()
[all …]
Dtest_uart_fifo.c4 * SPDX-License-Identifier: Apache-2.0
13 * - Test Steps
14 * - FIFO Output:
15 * -# Set UART IRQ callback using uart_irq_callback_set().
16 * -# Enable UART TX IRQ using uart_irq_tx_enable().
17 * -# Output the prepared data using uart_fifo_fill().
18 * -# Disable UART TX IRQ using uart_irq_tx_disable().
19 * -# Compare the number of characters sent out with the
21 * - FIFO Input:
22 * -# Set UART IRQ callback using uart_irq_callback_set().
[all …]
/Zephyr-Core-3.5.0/subsys/tracing/
Dtracing_backend_uart.c4 * SPDX-License-Identifier: Apache-2.0
7 /* Disable syscall tracing for all calls from this compilation unit to avoid
29 int rx; in uart_isr() local
41 rx = uart_fifo_read(dev, &byte, 1); in uart_isr()
42 if (rx < 0) { in uart_isr()
62 if (cur < length - 1) { in uart_isr()
/Zephyr-Core-3.5.0/boards/arm/teensy4/
Dteensy4-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1062dvl6a-pinctrl.dtsi>
18 drive-strength = "r0-5";
19 bias-pull-down;
20 bias-pull-down-value = "100k";
21 slew-rate = "fast";
22 nxp,speed = "200-mhz";
26 drive-strength = "r0-5";
27 bias-pull-up;
28 bias-pull-up-value = "22k";
[all …]
/Zephyr-Core-3.5.0/drivers/i2s/
Di2s_mcux_sai.c5 * SPDX-License-Identifier: Apache-2.0
22 #include <zephyr/dt-bindings/clock/imx_ccm.h>
52 * This indicates the Tx/Rx stream.
108 struct stream rx; member
126 while (k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT) == 0) { in i2s_purge_stream_buffers()
132 while (k_msgq_get(&strm->out_queue, &buffer, K_NO_WAIT) == 0) { in i2s_purge_stream_buffers()
140 struct i2s_dev_data *dev_data = dev->data; in i2s_tx_stream_disable()
141 struct stream *strm = &dev_data->tx; in i2s_tx_stream_disable()
142 const struct device *dev_dma = dev_data->dev_dma; in i2s_tx_stream_disable()
143 const struct i2s_mcux_config *dev_cfg = dev->config; in i2s_tx_stream_disable()
[all …]
/Zephyr-Core-3.5.0/subsys/bluetooth/controller/ll_sw/
Dull_df_internal.h2 * Copyright (c) 2018-2020 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
13 void ull_df_iq_report_mem_release(struct node_rx_hdr *rx);
22 /* Returns information if CTE sampling for periodic sync is requested to disable. */

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