Searched full:design (Results 1 – 25 of 298) sorted by relevance
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| /Zephyr-Core-3.5.0/boards/riscv/niosv_g/doc/ |
| D | index.rst | 9 niosv_g board is based on Intel FPGA Design Store Nios® V/g Hello World Example Design system and t…
17 Nios® V/g hello world example design system
20 Prebuilt Nios® V/g hello world example design system is available in Intel FPGA Design store.
21 …tel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html…
23 For example, Arria10 Nios® V/g processor example design system prebuilt files can be downloaded fro…
24 - https://www.intel.com/content/www/us/en/design-example/776196/intel-arria-10-fpga-hello-world-des…
26 ready_to_test/top.sof file is the prebuilt SRAM Object File for hello world example design system a…
28 Create Nios® V/g processor example design system in FPGA
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| /Zephyr-Core-3.5.0/boards/riscv/niosv_m/doc/ |
| D | index.rst | 9 niosv_m board is based on Intel FPGA Design Store Nios® V/m Hello World Example Design system and t…
17 Nios® V/m hello world example design system
20 Prebuilt Nios® V/m hello world example design system is available in Intel FPGA Design store.
21 …tel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html…
23 For example, Arria10 Nios® V/m processor example design system prebuilt files can be downloaded fro…
24 - https://www.intel.com/content/www/us/en/design-example/763960/arria10-niosv-based-helloworld-exam…
26 ready_to_test/top.sof file is the prebuilt SRAM Object File for hello world example design system a…
28 Create Nios® V/m processor example design system in FPGA
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| /Zephyr-Core-3.5.0/dts/bindings/sensor/ |
| D | maxim,max17055.yaml | 14 design-capacity:
17 description: The design capacity (aka label capacity) of the cell in mAh
19 design-voltage:
22 description: Battery Design Voltage in mV (3300 to 4400)
32 description: Battery Design Charging Current in mA (e.g. 2000)
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| D | maxim,max17262.yaml | 14 design-voltage:
17 description: Battery Design Voltage in mV (3300 to 4400)
27 description: Battery Design Charging Current in mA (e.g. 2000)
29 design-cap:
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| D | ti,bq274xx.yaml | 14 design-voltage:
17 description: Battery Design Voltage in mV (3300 - 4400)
19 design-capacity:
22 description: Battery Design Capacity in mAh
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| /Zephyr-Core-3.5.0/dts/bindings/lora/ |
| D | st,stm32wl-subghz-radio.yaml | 29 Maximum design power for the board's RFO_LP output matching network.
33 the board's RF design.
45 Maximum design power for the board's RFO_HP output matching network.
49 the board's RF design.
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| /Zephyr-Core-3.5.0/boards/arm/arty/doc/ |
| D | index.rst | 32 both the Cortex-M1 and the Cortex-M3 reference designs. The Cortex-M1 design
34 design only targets the Artix-7 based boards. Zephyr only supports the Artix-7
48 hardware features of the Cortex-M1 reference design:
69 supports the following hardware features of the Cortex-M3 reference design:
85 The Cortex-M1 reference design is configured to use the 100 MHz external
87 design is configured for 50MHz CPU system clock.
92 The reference design contains one Xilinx UART Lite. This UART is configured as
113 First, configure the FPGA with the selected reference design FPGA bitstream
115 Xilinx edition user guide (available as part of the reference design download
118 Another option for configuring the FPGA with the reference design bitstream is
[all …]
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| /Zephyr-Core-3.5.0/drivers/gpio/ |
| D | Kconfig.cmsdk_ahb | 1 # ARM CMSDK (Cortex-M System Design Kit) AHB GPIO cfg
7 bool "ARM CMSDK (Cortex-M System Design Kit) AHB GPIO Controllers"
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| /Zephyr-Core-3.5.0/drivers/i2c/ |
| D | Kconfig.dw | 5 bool "Design Ware I2C support"
9 Enable the Design Ware I2C driver
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| /Zephyr-Core-3.5.0/samples/sensor/max17262/ |
| D | app.overlay | 13 design-voltage = <3600>;
16 design-cap = <17000>;
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| /Zephyr-Core-3.5.0/soc/nios2/nios2f-zephyr/cpu/ |
| D | README | 1 These files are a Nios II/F CPU design provided by Altera for evaluating
2 Zephyr on Nios II. This design is intended for the Altera MAX10 10M50 Rec C
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| /Zephyr-Core-3.5.0/doc/security/ |
| D | secure-coding.rst | 33 We begin with an overview of secure design as it relates to
56 adhering to a defined set of design standards. In [SALT75]_, the following,
60 - **Open design** as a design guideline incorporates the maxim that
66 - **Economy of mechanism** specifies that the underlying design of a
138 how to design secure software.
140 This requires understanding the following design principles,
143 - economy of mechanism (keep the design as simple and small as
156 - open design (security mechanisms should not depend on attacker
157 ignorance of its design, but instead on more easily protected and
169 - least common mechanism (the design should minimize the mechanisms
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| /Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/common/ |
| D | Kconfig.soc | 131 …The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
139 The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
151 …User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
159 …User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
171 The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
175 For the reference hardware design, please refer to
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| /Zephyr-Core-3.5.0/drivers/sensor/max17055/ |
| D | max17055.h | 68 /* Design capacity in 5/Rsense uA */
76 /* The design capacity (aka label capacity) of the cell in mAh */
78 /* Design voltage of cell in mV */
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| /Zephyr-Core-3.5.0/doc/contribute/ |
| D | proposals_and_rfcs.rst | 10 design process and produce a consensus among the project stakeholders.
33 design while it's easier to change, before the design has been fully
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| /Zephyr-Core-3.5.0/doc/build/snippets/ |
| D | design.rst | 1 Snippets Design
4 This page documents design goals for the snippets feature.
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| /Zephyr-Core-3.5.0/doc/develop/west/ |
| D | why.rst | 12 During the development of west, a set of :ref:`west-design-constraints` were
43 Existing tools were considered during west's initial design and development.
85 .. _west-design-constraints:
87 Design Constraints
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| /Zephyr-Core-3.5.0/boards/xtensa/qemu_xtensa/ |
| D | Kconfig | 3 # Copyright (c) 2016 Cadence Design Systems, Inc.
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| /Zephyr-Core-3.5.0/boards/xtensa/xt-sim/ |
| D | Kconfig.defconfig | 1 # Copyright (c) 2016 Cadence Design Systems, Inc.
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| D | Kconfig.board | 3 # Copyright (c) 2016 Cadence Design Systems, Inc.
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| /Zephyr-Core-3.5.0/drivers/spi/ |
| D | Kconfig.bitbang | 1 # Copyright (c) 2021, Marc Reilly, Creative Product Design
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| /Zephyr-Core-3.5.0/doc/build/dts/ |
| D | design.rst | 1 .. _dt-design:
3 Design goals
7 changes are expected. The following are the general design goals, along with
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| /Zephyr-Core-3.5.0/doc/hardware/peripherals/ |
| D | w1.rst | 94 https://www.maximintegrated.com/en/design/technical-documents/app-notes/9/937.html
97 https://www.maximintegrated.com/en/design/technical-documents/app-notes/1/155.html
100 https://www.maximintegrated.com/en/design/technical-documents/app-notes/1/187.html
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| /Zephyr-Core-3.5.0/soc/xtensa/sample_controller/ |
| D | Kconfig.defconfig | 4 # Copyright (c) 2016 Cadence Design Systems, Inc.
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| D | linker.ld | 2 * Copyright (c) 2016 Cadence Design Systems, Inc.
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