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/Zephyr-Core-3.5.0/dts/bindings/mtd/
Datmel,at45.yaml61 When set, the driver will use the Ultra-Deep Power-Down command instead
62 of the default Deep Power-Down one to put the chip into low power mode.
65 SRAM buffers in the chip, the difference between the Deep and Ultra-Deep
73 Time, in nanoseconds, needed by the chip to enter the Deep Power-Down
74 mode (or Ultra-Deep Power-Down mode when the "use-udpd" property is set)
81 Time, in nanoseconds, needed by the chip to exit from the Deep Power-Down
82 mode (or Ultra-Deep Power-Down mode when the "use-udpd" property is set)
Djedec,spi-nor-common.yaml32 Use this property to indicate the flash chip supports the Deep
35 implies that the RDPD (0xAB) Release from Deep Power Down command
44 Some devices (Macronix MX25R in particular) wake from deep power
48 (1) tDPDD (Delay Time for Release from Deep Power-Down Mode)
49 (2) tCDRP (CSn Toggling Time before Release from Deep Power-Down Mode)
50 (3) tRDP (Recovery Time for Release from Deep Power-Down Mode)
53 used to wake the chip from Deep Power-Down mode.
62 deep power down.
73 deep power down and be ready to receive additional commands.
/Zephyr-Core-3.5.0/tests/subsys/pm/power_mgmt_soc/src/
Dpower_mgmt.h11 /** @brief Alternates between light and deep sleep cycles.
16 * Similarly for deep sleep, the test sleeps in the main thread for 500 ms
24 /** @brief Alternates between light and deep sleep cycles.
26 * Performs same approach to achieve light and deep sleep, but additional
36 * Performs a dummy initialization for the board to enter light/deep sleep
Dpower_mgmt.c28 * and not accidentally into a deep sleep.
29 * - for deep sleep it can be very long as we want to ensure that we enter
250 /* Deep sleep cycle */ in test_pwr_mgmt_multithread()
251 /* Platforms that do not automatically enter deep sleep */ in test_pwr_mgmt_multithread()
256 LOG_INF("About to enter deep sleep"); in test_pwr_mgmt_multithread()
264 LOG_INF("Wake from Deep Sleep"); in test_pwr_mgmt_multithread()
299 /* Trigger Deep Sleep 1 state. 48MHz PLL off */ in test_pwr_mgmt_singlethread()
300 /* Platforms that do not automatically enter deep sleep */ in test_pwr_mgmt_singlethread()
303 LOG_INF("About to enter deep Sleep"); in test_pwr_mgmt_singlethread()
309 LOG_INF("Wake from Deep Sleep"); in test_pwr_mgmt_singlethread()
[all …]
/Zephyr-Core-3.5.0/samples/boards/mec15xxevb_assy6853/power_management/src/
Dpower_mgmt.h11 /** @brief Alternates between light and deep sleep cycles.
16 * Similarly for deep sleep, the test sleeps in the main thread for 500 ms
26 /** @brief Alternates between light and deep sleep cycles.
28 * Performs same approach to achieve light and deep sleep, but additional
Dpower_mgmt.c66 * JP25.5 (GPIO013_DP) deep sleep
267 /* Ensure we can enter deep sleep when stopping threads in test_pwr_mgmt_multithread()
299 /* Deep sleep cycle */ in test_pwr_mgmt_multithread()
302 LOG_INF("About to enter deep sleep"); in test_pwr_mgmt_multithread()
304 /* GPIO toggle to measure latency for deep sleep */ in test_pwr_mgmt_multithread()
312 LOG_INF("Wake from Deep Sleep"); in test_pwr_mgmt_multithread()
314 printk("Wake from Deep Sleep\n"); in test_pwr_mgmt_multithread()
355 /* Trigger Deep Sleep 1 state. 48MHz PLL off */ in test_pwr_mgmt_singlethread()
356 LOG_INF("About to enter deep Sleep"); in test_pwr_mgmt_singlethread()
366 LOG_INF("Wake from Deep Sleep"); in test_pwr_mgmt_singlethread()
[all …]
/Zephyr-Core-3.5.0/dts/bindings/power/
Dnxp,pdcfg-power.yaml11 deep-sleep-config:
15 power to various blocks while the CPU is in deep sleep mode. These values
16 are programmed to the sleep configuration registers before entering deep
/Zephyr-Core-3.5.0/soc/arm/nuvoton_npcx/common/
Dpower.c23 * | Deep Sleep | On | Stop | Stop | Stop | Power Down | On | On |
32 * - A delay of 'Instant' wake-up from 'Deep Sleep' is 20 us.
33 * - A delay of 'Standard' wake-up from 'Deep Sleep' is 3.43 ms.
34 * - Max residency time in Deep Sleep for 'Instant' wake-up is 200 ms
35 * - Min Residency time in Deep Sleep for 'Instant' wake-up is 61 us
40 * Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency time
42 * Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency time
62 /* The steps that npcx ec enters sleep/deep mode and leaves it. */
104 * save power consumption when ec enter deep sleep.
151 /* Configure sleep/deep sleep settings in clock control module. */ in npcx_power_enter_system_sleep()
[all …]
Dsoc_clock.h170 * low-frequency timer before ec entered deep idle state.
176 * system timer by low-frequency timer after ec left deep idle state.
182 * @brief Function to get time ticks in system sleep/deep sleep state. The unit
190 * instruction, ec will enter sleep/deep sleep state for better power
193 * @param is_deep A boolean indicating ec enters deep sleep or sleep state
194 * @param is_instant A boolean indicating 'Instant Wake-up' from deep idle is
/Zephyr-Core-3.5.0/soc/riscv/riscv-ite/common/
Dpower.c11 /* Handle when enter deep doze mode. */
14 /* Enter deep doze mode */ in ite_power_soc_deep_doze()
24 /* Deep doze mode */ in pm_state_set()
/Zephyr-Core-3.5.0/samples/boards/mec15xxevb_assy6853/power_management/
DREADME.rst10 It showcase simple app that allows to enter into light and deep sleep.
25 Wake from Deep Sleep
29 Wake from Deep Sleep
Dsample.yaml15 - "Wake from Deep Sleep"
/Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/esp32/
DKconfig.soc90 - "Internal 150kHz oscillator" option provides lowest deep sleep current
93 drift in deep/light sleep modes.
95 expense of slightly higher (1uA) deep sleep current consumption.
104 deep sleep current (by 5uA) but has better frequency stability than
135 time in deep sleep. Lower numbers reduce startup time.
156 int "Extra delay in deep sleep wake stub (in us)"
160 When ESP32 exits deep sleep, the CPU and the flash chip are powered on
161 at the same time. CPU will run deep sleep stub first, and then
171 console after deep sleep reset, try increasing this value.
/Zephyr-Core-3.5.0/samples/boards/esp32/deep_sleep/
DREADME.rst1 .. _esp32-deep-sleep-sample:
3 ESP32 Deep Sleep demo
9 The deep sleep mode of the ESP32 Series is a power saving mode that causes the
13 This sample shows how to set a wake up source, trigger deep sleep and then
28 as wake-up source, deep sleep for 20 seconds, wake up.
DKconfig4 mainmenu "Espressif Deep Sleep demo"
10 This option enables wake up from deep sleep from GPIO2 and
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/
Ddevice_power.h16 * Disable UART deep sleep save/restore. If a UART TX FIFO has data on deep
26 * prior to deep sleep entry.
Dpower.c25 * Deep Sleep
67 * Enable deep sleep mode in CM4 and MEC172x. in z_power_soc_deep_sleep()
68 * Enable CM4 deep sleep and sleep signals assertion on WFI. in z_power_soc_deep_sleep()
144 * For deep sleep pm_system_suspend has executed all the driver
166 * >= numerical priority. MCHP z_power_soc_(deep)_sleep sets PRIMASK=1 and BASEPRI=0
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec1501/
Dpower.c17 * Deep Sleep
74 * after exiting deep sleep, so need to unmask exceptions in z_power_soc_deep_sleep()
102 * For deep sleep pm_system_suspend has executed all the driver
124 * preventing wake. MCHP z_power_soc_(deep)_sleep sets PRIMASK=1 and BASEPRI=0
/Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/esp32s2/
DKconfig.soc65 - "Internal 90kHz oscillator" option provides lowest deep sleep current
68 drift in deep/light sleep modes.
70 expense of slightly higher (1uA) deep sleep current consumption.
79 deep sleep current (by 5uA) but has better frequency stability than
109 time in deep sleep. Lower numbers reduce startup time.
/Zephyr-Core-3.5.0/soc/arm/nxp_kinetis/ke1xf/
Dpower.c35 /* Set partial stop mode and enable deep sleep */ in pm_state_set()
59 /* Disable deep sleep upon exit */ in pm_state_exit_post_ops()
/Zephyr-Core-3.5.0/samples/boards/esp32/light_sleep/
Dprj.conf2 # Required to disable default behavior of deep sleep on timeout
/Zephyr-Core-3.5.0/soc/arm/arm/beetle/
Dsoc_registers.h59 /* Offset: 0x090 (r/w) AHB peripheral clock set in deep sleep state */
61 /* Offset: 0x094 (r/w) AHB peripheral clock clear in deep sleep state */
72 /* Offset: 0x0b0 (r/w) APB peripheral clock set in deep sleep state */
74 /* Offset: 0x0b4 (r/w) APB peripheral clock clear in deep sleep state */
/Zephyr-Core-3.5.0/drivers/flash/
DKconfig.nor67 bool "Use Deep Power-Down mode when flash is not being accessed."
69 Where supported deep power-down mode can reduce current draw
/Zephyr-Core-3.5.0/samples/boards/mimxrt595_evk_cm33/system_off/
Dsample.yaml7 name: Deep Power Down State Sample for mimxrt595_evk
/Zephyr-Core-3.5.0/boards/arm/mimxrt595_evk/
DKconfig.defconfig34 # when transitioning the SoC to Deep Low Power modes.

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