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/Zephyr-Core-3.5.0/dts/bindings/serial/
Dst,stm32-uart-base.yaml2 # SPDX-License-Identifier: Apache-2.0
5 description: STM32 UART-BASE
7 include: [uart-controller.yaml, pinctrl-device.yaml, reset-device.yaml]
22 single-wire:
25 Enable the single wire half-duplex communication.
30 tx-rx-swap:
35 tx-invert:
41 rx-invert:
47 pinctrl-0:
50 pinctrl-names:
[all …]
Dnxp,kinetis-lpuart.yaml3 compatible: "nxp,kinetis-lpuart"
5 include: [uart-controller.yaml, pinctrl-device.yaml]
17 Enable loopback mode on LPUART peripheral. When present, RX pin is
21 nxp,rs485-mode:
24 Set to enable RTS signal, which can be used to enable the driver
25 of an external RS-485 transceiver. Note hw-flow-control should be
28 nxp,rs485-de-active-low:
/Zephyr-Core-3.5.0/dts/bindings/misc/
Dzephyr,modbus-serial.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "zephyr,modbus-serial"
8 include: uart-device.yaml
11 de-gpios:
12 type: phandle-array
13 description: Driver enable pin.
15 Driver enable pin (DE) of the RS-485 transceiver.
19 re-gpios:
20 type: phandle-array
21 description: Receiver enable pin.
[all …]
/Zephyr-Core-3.5.0/drivers/serial/
Duart_stm32.h2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
4 * SPDX-License-Identifier: Apache-2.0
36 /* switch to enable single wire / half duplex feature */
38 /* enable tx/rx pin swap */
40 /* enable rx pin inversion */
42 /* enable tx pin inversion */
44 /* enable de signal */
46 /* de signal assertion time in 1/16 of a bit */
48 /* de signal deassertion time in 1/16 of a bit */
50 /* enable de pin inversion */
[all …]
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/common/
Dsoc_gpio.c3 * SPDX-License-Identifier: Apache-2.0
27 pio->PIO_IDR = mask; in configure_common_attr()
29 /* Configure pull-up(s) */ in configure_common_attr()
31 pio->PIO_PUER = mask; in configure_common_attr()
33 pio->PIO_PUDR = mask; in configure_common_attr()
36 /* Configure pull-down only for MCU series that support it */ in configure_common_attr()
38 /* Configure pull-down(s) */ in configure_common_attr()
40 pio->PIO_PPDER = mask; in configure_common_attr()
42 pio->PIO_PPDDR = mask; in configure_common_attr()
46 /* Configure open drain (multi-drive) */ in configure_common_attr()
[all …]
Dsoc_sam4l_gpio.c3 * SPDX-License-Identifier: Apache-2.0
7 * @brief Atmel SAM MCU family General-Purpose Input/Output Controller (GPIO)
20 gpio->IERC = mask; in configure_common_attr()
22 /* Configure pull-up(s) */ in configure_common_attr()
24 gpio->PUERS = mask; in configure_common_attr()
26 gpio->PUERC = mask; in configure_common_attr()
29 /* Configure pull-down(s) */ in configure_common_attr()
31 gpio->PDERS = mask; in configure_common_attr()
33 gpio->PDERC = mask; in configure_common_attr()
36 /* Configure open drain (multi-drive) */ in configure_common_attr()
[all …]
/Zephyr-Core-3.5.0/boards/arm/am62x_m4/
Dam62x_m4_phyboard_lyra_defconfig1 # PHYTEC AM62x M4 phyBOARD-Lyra
4 # Author: Daniel Schultz <d.schultz@phytec.de>
6 # SPDX-License-Identifier: Apache-2.0
17 # Enable Pinctrl
23 # Enable Console
/Zephyr-Core-3.5.0/drivers/adc/
DKconfig.esp321 # Copyright (c) 2022 Wolter HV <wolterhv@gmx.de>
3 # SPDX-License-Identifier: Apache-2.0
10 Enable the driver implementation for the ESP32 ADC
/Zephyr-Core-3.5.0/drivers/crypto/
DKconfig.stm323 # Copyright (c) 2020 Markus Fuchs <markus.fuchs@de.sauter-bc.com>
4 # SPDX-License-Identifier: Apache-2.0
13 Enable STM32 HAL-based Cryptographic Accelerator driver.
/Zephyr-Core-3.5.0/drivers/sensor/ms5607/
DKconfig3 # Copyright (c) 2019 Thomas Schmid <tom@lfence.de>
4 # SPDX-License-Identifier: Apache-2.0
13 Enable driver for MS5607 pressure and temperature sensor.
/Zephyr-Core-3.5.0/modules/openthread/
DKconfig.thread4 # SPDX-License-Identifier: Apache-2.0
22 default "de:ad:00:be:ef:00:ca:fe"
25 format "de:ad:00:be:ef:00:ca:fe"
48 bool "FTD - Full Thread Device"
50 bool "MTD - Minimal Thread Device"
54 bool "SED - Sleepy End Device"
74 string "The platform-specific string to insert into the OpenThread version string"
124 router, enable the Inform Previous Parent on Reattach feature.
131 to the network—enable the Periodic Parent Search feature.
145 default -65
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/Zephyr-Core-3.5.0/dts/bindings/mipi-dsi/
Dst,stm32-mipi-dsi.yaml4 # SPDX-License-Identifier: Apache-2.0
9 compatible: "st,stm32-mipi-dsi"
11 include: [mipi-dsi-host.yaml, reset-device.yaml]
17 clock-names:
20 "dsiclk" DSI clock enable.
28 hs-active-high:
33 vs-active-high:
38 de-active-high:
41 DSI host data enable is active high.
43 non-continuous:
[all …]
/Zephyr-Core-3.5.0/drivers/ethernet/
DKconfig.dsa4 # Lukasz Majewski <lukma@denx.de>
5 # SPDX-License-Identifier: Apache-2.0
11 Enable Distributed Switch Architecture support. For now it
50 module-dep = NET_LOG
51 module-str = Log level for DSA
52 module-help = Enables core DSA code to output debug messages.
/Zephyr-Core-3.5.0/lib/os/
DKconfig.heap3 # SPDX-License-Identifier: Apache-2.0
42 such as memory allocation and de-allocation.
47 Hidden option to enable API for registering and notifying
57 Heaps using reduced-size chunk headers can accommodate so called
60 Heaps using full-size chunk headers can have a total size up to
63 On 32-bit system the tradeoff is selectable between:
65 - "small" heaps with low memory and runtime overhead;
67 - "big" heaps with bigger memory overhead even for small heaps;
69 - "auto" providing optimal memory overhead in all cases but with
72 On 64-bit systems the "big" chunk header size conveniently provides
[all …]
/Zephyr-Core-3.5.0/dts/bindings/display/panel/
Dpanel-timing.yaml2 # SPDX-License-Identifier: Apache-2.0
9 a panel under display-timings node. For example:
12 display-timings {
13 compatible = "zephyr,panel-timing";
14 hsync-len = <8>;
15 hfront-porch = <32>;
16 hback-porch = <32>;
17 vsync-len = <2>;
18 vfront-porch = <16>;
19 vback-porch = <14>;
[all …]
/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_andes_atcgpio100.c4 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/dt-bindings/gpio/andestech-atcgpio100.h>
34 #define REG_PUEN 0x40 /* Pull enable reg. */
36 #define REG_INTE 0x50 /* Interrupt enable reg. */
42 #define REG_DEBE 0x70 /* De-bounce enable reg. */
43 #define REG_DEBC 0x74 /* De-Bounce control reg. */
57 ((const struct gpio_atcgpio100_config * const)(dev)->config)->base
102 struct gpio_atcgpio100_data * const data = port->data; in gpio_atcgpio100_config()
112 return -ENOTSUP; in gpio_atcgpio100_config()
125 key = k_spin_lock(&data->lock); in gpio_atcgpio100_config()
[all …]
/Zephyr-Core-3.5.0/tests/kernel/obj_core/obj_core_stats_api/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
39 * Attempt to enable stats for an object core that is not enabled in ZTEST()
44 zassert_equal(status, -ENOTSUP, in ZTEST()
45 "Expected %d, got %d\n", -ENOTSUP, status); in ZTEST()
47 saved_enable = K_OBJ_CORE(test_thread)->type->stats_desc->enable; in ZTEST()
48 K_OBJ_CORE(test_thread)->type->stats_desc->enable = NULL; in ZTEST()
50 zassert_equal(status, -ENOTSUP, in ZTEST()
51 "Expected %d, got %d\n", -ENOTSUP, status); in ZTEST()
52 K_OBJ_CORE(test_thread)->type->stats_desc->enable = saved_enable; in ZTEST()
55 * Note: Testing the stats enable function pointer is done in another in ZTEST()
[all …]
/Zephyr-Core-3.5.0/subsys/modbus/
Dmodbus_internal.h5 * SPDX-License-Identifier: Apache-2.0
14 * Copyright 2003-2020 Silicon Laboratories Inc. www.silabs.com
16 * SPDX-License-Identifier: APACHE-2.0
20 * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
49 /* Diagnostic sub-function codes */
74 /* RTU timeout (maximum inter-frame delay) */
78 /* Pointer to driver enable (DE) pin config */
79 struct gpio_dt_spec *de; member
80 /* Pointer to receiver enable (nRE) pin config */
172 * -ENOTSUP if Modbus mode is not supported,
[all …]
/Zephyr-Core-3.5.0/boards/shields/rk055hdmipi4ma0/
Drk055hdmipi4ma0.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
14 en_mipi_display_rk055hdmipi4ma0: enable-mipi-display-rk055hdmipi4ma0 {
15 compatible = "regulator-fixed";
16 regulator-name = "en_mipi_display";
17 enable-gpios = <&nxp_mipi_connector 32 GPIO_ACTIVE_HIGH>;
18 regulator-boot-on;
22 compatible = "zephyr,lvgl-pointer-input";
29 gt911_rk055hdmipi4ma0: gt911-rk055hdmipi4ma0@5d {
32 irq-gpios = <&nxp_mipi_connector 29 GPIO_ACTIVE_HIGH>;
[all …]
/Zephyr-Core-3.5.0/boards/shields/rk055hdmipi4m/
Drk055hdmipi4m.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
14 en_mipi_display: enable-mipi-display {
15 compatible = "regulator-fixed";
16 regulator-name = "en_mipi_display";
17 enable-gpios = <&nxp_mipi_connector 32 GPIO_ACTIVE_HIGH>;
18 regulator-boot-on;
22 compatible = "zephyr,lvgl-pointer-input";
32 irq-gpios = <&nxp_mipi_connector 29 GPIO_ACTIVE_HIGH>;
33 reset-gpios = <&nxp_mipi_connector 28 GPIO_ACTIVE_HIGH>;
[all …]
/Zephyr-Core-3.5.0/subsys/net/l2/ieee802154/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
18 module-dep = NET_LOG
19 module-str = Log level for IEEE 802.15.4
20 module-help = Enables IEEE 802.15.4 code to output debug messages.
27 Enable printing out in/out 802.15.4 packets. This is extremely
28 verbose, do not enable this unless you know what you are doing.
31 prompt "Which packet do you want to print-out?"
36 bool "Print-out both RX and TX packets"
38 This will print-out both received and transmitted packets.
41 bool "Print-out only RX packets"
[all …]
/Zephyr-Core-3.5.0/boards/arm/beagle_bcf/
Dboard_antenna.c1 /* SPDX-License-Identifier: Apache-2.0
9 * Implements the RF driver callback to configure the on-board antenna
62 /* Switch off all paths first. Needs to be done anyway in every sub-case below. */ in board_cc13xx_rf_callback()
73 switch (setupCommand->common.commandNo) { in board_cc13xx_rf_callback()
76 loDivider = RF_LODIVIDER_MASK & setupCommand->common.loDivider; in board_cc13xx_rf_callback()
77 /* Sub-1GHz front-end. */ in board_cc13xx_rf_callback()
82 loDivider = RF_LODIVIDER_MASK & setupCommand->prop_div.loDivider; in board_cc13xx_rf_callback()
83 /* Sub-1GHz front-end. */ in board_cc13xx_rf_callback()
91 /* Sub-1 GHz */ in board_cc13xx_rf_callback()
93 /* PA enable --> HIGH PA */ in board_cc13xx_rf_callback()
[all …]
/Zephyr-Core-3.5.0/drivers/entropy/
Dentropy_cc13xx_cc26xx.c4 * SPDX-License-Identifier: Apache-2.0
52 /* De-tune FROs */ in start_trng()
55 /* Enable FROs */ in start_trng()
87 /* De-tune FROs */ in handle_shutdown_ovf()
89 /* Re-enable FROs */ in handle_shutdown_ovf()
97 struct entropy_cc13xx_cc26xx_data *data = dev->data; in entropy_cc13xx_cc26xx_get_entropy()
103 if (!data->constrained) { in entropy_cc13xx_cc26xx_get_entropy()
105 data->constrained = true; in entropy_cc13xx_cc26xx_get_entropy()
113 k_sem_take(&data->lock, K_FOREVER); in entropy_cc13xx_cc26xx_get_entropy()
114 cnt = ring_buf_get(&data->pool, buf, len); in entropy_cc13xx_cc26xx_get_entropy()
[all …]
/Zephyr-Core-3.5.0/soc/x86/apollo_lake/doc/
Dsupported_features.txt5 etc.), Zephyr supports the following Apollo Lake-specific SoC devices:
13 HSUART High-Speed Serial Port Support
14 -------------------------------------
16 The Apollo Lake UARTs are NS16550-compatible, with "high-speed" capability.
20 in turn outputs the baud master clock. The PLL is controlled by a per-UART
21 32-bit register called ``PRV_CLOCK_PARAMS`` (aka the ``PCP``), the format of
24 +--------+---------+--------+--------+
27 | enable | ``m`` | ``n`` | toggle |
28 +--------+---------+--------+--------+
34 results in the de-facto standard 1.8432MHz master clock and a max baud rate
[all …]
/Zephyr-Core-3.5.0/boards/arm/nucleo_f031k6/
Dnucleo_f031k6.dts2 * Copyright (c) 2021 Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f0/stm32f031k6tx-pinctrl.dtsi>
12 model = "STMicroelectronics STM32F031K6-NUCLEO board";
13 compatible = "st,stm32f031k6-nucleo";
17 zephyr,shell-uart = &usart1;
23 compatible = "gpio-leds";
31 compatible = "pwm-leds";
39 pwm-led0 = &green_pwm_led;
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