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/Zephyr-latest/kernel/
DKconfig.smp36 By default Zephyr will boot all available CPUs during start up.
38 (architecture/SoC/board/application) to boot secondary CPUs at
42 int "Maximum number of CPUs/cores"
53 to broadcast an interrupt that will call z_sched_ipi() on other CPUs
65 restricted by its CPU mask to execute on a subset of all CPUs) may
86 set of CPUs that need an IPI to trigger a reschedule in response to
89 O(N) in the number of CPUs, and in exchange reduces the number of
92 IPIs to specific CPUs then this has the potential to significantly
94 system as the number of CPUs increases. If not, the only benefit
96 lower priority than all the threads currently executing on other CPUs.
[all …]
Dsmp.c183 * across all CPUs using the start_flag. So just set it to 1. in k_smp_cpu_start()
212 * across all CPUs using the start_flag. So just set it to 1. in k_smp_cpu_resume()
224 /* We are powering up all CPUs and we want to synchronize their in z_smp_init()
229 /* Just start CPUs one by one. */ in z_smp_init()
237 /* Let loose those CPUs so they can start scheduling in z_smp_init()
/Zephyr-latest/subsys/pm/
Dstate.c11 BUILD_ASSERT(DT_NODE_EXISTS(DT_PATH(cpus)),
12 "cpus node not defined in Devicetree");
40 DT_FOREACH_CHILD(DT_PATH(cpus), CHECK_POWER_STATES_CONSISTENCY)
47 DT_FOREACH_CHILD(DT_PATH(cpus), DEFINE_CPU_STATES);
51 DT_FOREACH_CHILD_STATUS_OKAY_SEP(DT_PATH(cpus), CPU_STATE_REF, (,))
56 DT_FOREACH_CHILD_STATUS_OKAY_SEP(DT_PATH(cpus), DT_NUM_CPU_POWER_STATES, (,))
/Zephyr-latest/soc/telink/tlsr/tlsr951x/
Dsoc.c60 #if ((DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_16MHZ) && \
61 (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_24MHZ) && \
62 (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_32MHZ) && \
63 (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_48MHZ) && \
64 (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_64MHZ) && \
65 (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_96MHZ))
76 unsigned int cclk = DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency); in soc_early_init_hook()
/Zephyr-latest/arch/riscv/include/
Dkernel_arch_func.h35 csr_write(mscratch, &_kernel.cpus[0]); in arch_kernel_init()
38 _kernel.cpus[0].arch.hartid = csr_read(mhartid); in arch_kernel_init()
39 _kernel.cpus[0].arch.online = true; in arch_kernel_init()
43 DT_FOREACH_CHILD_STATUS_OKAY_SEP(DT_PATH(cpus), DT_REG_ADDR, (,)) in arch_kernel_init()
48 if (cpu_node_list[hart_x] == _kernel.cpus[0].arch.hartid) { in arch_kernel_init()
51 _kernel.cpus[cpu_num].arch.hartid = cpu_node_list[hart_x]; in arch_kernel_init()
93 return _kernel.cpus[0].nested != 0U; in arch_is_in_isr()
/Zephyr-latest/drivers/led_strip/
DKconfig.ws281256 default $(div,$(mul,700,$(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)),1000000000) \
57 if $(dt_node_has_prop,/cpus/cpu@0,clock-frequency)
66 default $(div,$(mul,600,$(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)),1000000000) \
67 if $(dt_node_has_prop,/cpus/cpu@0,clock-frequency)
76 default $(div,$(mul,350,$(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)),1000000000) \
77 if $(dt_node_has_prop,/cpus/cpu@0,clock-frequency)
86 default $(div,$(mul,800,$(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)),1000000000) \
87 if $(dt_node_has_prop,/cpus/cpu@0,clock-frequency)
/Zephyr-latest/doc/kernel/services/smp/
Dsmp.rst7 physical CPUs running Zephyr application code. This support is
20 number of physical CPUs available is visible at build time as
22 number of available CPUs on the platform and it is not expected that
62 subsystems or data structures, preventing CPUs from contending on a
83 threads. The kernel will ensure that only one thread across all CPUs
86 when a thread is switched in. Other CPUs will spin waiting for the
100 partition work across physical CPUs instead of relying solely on the
103 kconfig variable, which can associate a specific set of CPUs with each
104 thread, indicating on which CPUs it can run.
128 Auxiliary CPUs begin in a disabled state in the architecture layer.
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/Zephyr-latest/tests/subsys/zbus/hlp_priority_boost/
Dtestcase.yaml6 # between CPUs. So the zbus_channel struct data goes
7 # out-of-sync between CPUs with multiple producer and
8 # consumer threads running concurrently on multiple CPUs,
/Zephyr-latest/dts/bindings/cpu/
Dsifive-common.yaml4 # Common fields for SiFive RISC-V CPUs
6 include: riscv,cpus.yaml
Dtelink,b91.yaml8 include: riscv,cpus.yaml
Dintel,niosv.yaml8 include: riscv,cpus.yaml
Dsensry,ganymed-sy1xx.yaml4 include: riscv,cpus.yaml
Dopenisa,ri5cy.yaml9 include: riscv,cpus.yaml
Dlowrisc,ibex.yaml9 include: riscv,cpus.yaml
/Zephyr-latest/tests/kernel/ipi_cascade/src/
Dmain.c8 * This test is intended to run on an SMP platform with 2 CPUs. It engineers
10 * 3rd highest priority threads will be scheduled to execute on the 2 CPUs
25 * leaving T3 and T1 executing on the 2 CPUs. However, this final step will
80 str, _kernel.cpus[0].current, in show_executing_threads()
81 _kernel.cpus[0].current->name, in show_executing_threads()
82 _kernel.cpus[0].current->base.prio); in show_executing_threads()
84 str, _kernel.cpus[1].current, in show_executing_threads()
85 _kernel.cpus[1].current->name, in show_executing_threads()
86 _kernel.cpus[1].current->base.prio); in show_executing_threads()
253 "Main thread (T1) did not change CPUs\n"); in ZTEST()
/Zephyr-latest/arch/riscv/core/
Dsmp.c48 riscv_cpu_wake_flag = _kernel.cpus[cpu_num].arch.hartid; in arch_cpu_start()
58 if (_kernel.cpus[i].arch.hartid == hartid) { in arch_secondary_cpu_init()
62 csr_write(mscratch, &_kernel.cpus[cpu_num]); in arch_secondary_cpu_init()
64 _kernel.cpus[cpu_num].arch.online = true; in arch_secondary_cpu_init()
Dipi_clint.c30 if ((i != id) && _kernel.cpus[i].arch.online && ((cpu_bitmap & BIT(i)) != 0)) { in arch_sched_directed_ipi()
32 MSIP(_kernel.cpus[i].arch.hartid) = 1; in arch_sched_directed_ipi()
43 MSIP(_kernel.cpus[cpu].arch.hartid) = 1; in arch_flush_fpu_ipi()
/Zephyr-latest/soc/andestech/ae350/
Dpma.h12 * We should configure CSRs of all CPUs to make memory attribute
13 * (e.g. uncacheable) affects all CPUs.
/Zephyr-latest/dts/bindings/pwm/
Dfsl,imx27-pwm.yaml7 same module present starting from imx27 CPUs and this driver can potentially
8 support other CPUs with imx27 module. This is also the same string used
/Zephyr-latest/include/zephyr/arch/arc/
Darch_inlines.h24 return &_kernel.cpus[core]; in arch_curr_cpu()
26 return &_kernel.cpus[0]; in arch_curr_cpu()
/Zephyr-latest/soc/espressif/common/
DKconfig.defconfig26 default $(dt_node_int_prop_int,/cpus/cpu@0,xtal-freq)
81 default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
/Zephyr-latest/arch/arm64/core/
Dprep_c.c40 write_tpidrro_el0((uintptr_t)&_kernel.cpus[0]); in z_prep_c()
45 /* After bss clean, _kernel.cpus is in bss section */ in z_prep_c()
/Zephyr-latest/subsys/logging/backends/
DKconfig.swo16 …default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if $(dt_node_has_prop,/cpus/cpu@0,cloc…
/Zephyr-latest/tests/kernel/mp/src/
Dmain.c12 #error Cannot test MP API if SMP is using the CPUs
58 * CPUs on SMP systems.
95 * scenario which own over two CPUs.
/Zephyr-latest/boards/microchip/m2gl025_miv/support/
Dm2gl025_miv.repl3 using "platforms/cpus/miv.repl"

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