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/Zephyr-Core-3.5.0/tests/posix/pthread_pressure/src/
Dmain.c39 static uint64_t counters[NUM_THREADS]; variable
46 printk("Thread %d created and joined %llu times (%llu joins/s)\n", i, counters[i], in print_stats()
47 (counters[i] - prev_counters[i]) / UPDATE_INTERVAL_S); in print_stats()
48 prev_counters[i] = counters[i]; in print_stats()
72 zassert_ok(ret, "%s_create(%d)[%zu] failed: %d", tag, i, counters[i], ret); in test_create_join_common()
87 counters[i], ret); in test_create_join_common()
92 ++counters[i]; in test_create_join_common()
103 counters[i], ret); in test_create_join_common()
118 zassert_true(counters[i] > 0, "%s %d was never scheduled", in test_create_join_common()
227 counters[i] = 0; in before()
/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/neorv32/
Dreset.S28 /* Allow mcycle and minstret counters to increment */
32 /* Zerorize counters */
/Zephyr-Core-3.5.0/dts/bindings/counter/
Dst,stm32-counter.yaml4 description: STM32 counters
Dinfineon,cat1-counter.yaml6 description: Infineon counters
/Zephyr-Core-3.5.0/subsys/testsuite/coverage/
Dcoverage.h70 /**Information about counters for a single function
87 * idiom. The number of counters is determined from the merge pointer
97 struct gcov_ctr_info ctrs[1]; /* instrumented counters */
/Zephyr-Core-3.5.0/boards/arm/stm32h7b3i_dk/support/
Dopenocd.cfg11 # Stop Watchdog counters when halt
/Zephyr-Core-3.5.0/soc/arm/nuvoton_npcx/common/
Dsoc_dbg.h16 * the Core is halted, various modules’ clocks, counters are stopped and
/Zephyr-Core-3.5.0/soc/arm/arm/mps3/
Dsoc.h21 #define __PMU_NUM_EVENTCNT 8U /* PMU Event Counters */
/Zephyr-Core-3.5.0/boards/arm/b_u585i_iot02a/support/
Dopenocd.cfg13 # Stop Watchdog counters when halt
/Zephyr-Core-3.5.0/boards/arm/nucleo_u575zi_q/support/
Dopenocd.cfg13 # Stop Watchdog counters when halt
/Zephyr-Core-3.5.0/boards/arm/nucleo_u5a5zj_q/support/
Dopenocd.cfg13 # Stop Watchdog counters when halt
/Zephyr-Core-3.5.0/subsys/stats/
DKconfig8 Enable per-module event counters for troubleshooting, maintenance,
/Zephyr-Core-3.5.0/drivers/counter/
Dcounter_mchp_xec.c13 * This is the driver for the 16/32-bit counters on the Microchip SoCs.
16 * - The counters are running in down counting mode.
19 * - These are not free running counters where there are separate
22 * when the counters reach zero.
/Zephyr-Core-3.5.0/tests/kernel/common/src/
Dboot_delay.c22 /* Systems with very fast counters (like the x86 TSC) in ZTEST()
/Zephyr-Core-3.5.0/tests/subsys/pm/power_mgmt_soc/src/
Dpower_mgmt.h38 * on the board. Also serves to initialize the counters.
/Zephyr-Core-3.5.0/doc/hardware/peripherals/
Drtc.rst23 It should not be confused with low-power counters which sometimes share
41 The disadvantages of this approach were that hardware counters could
/Zephyr-Core-3.5.0/dts/bindings/sensor/
Dnxp,mcux-qdec.yaml46 difference counters to operate with count rates up to the IPBus
/Zephyr-Core-3.5.0/subsys/usb/usb_c/
Dusbc_prl.h57 /* Counters */
59 /** message id counters for all 6 port partners */
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/reg/
Dmec_pwm.h28 * Enable and start PWM. Clearing this bit resets internal counters.
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/
Ddevice_power.h39 * timers, counters, UART, etc. We save the enables for these
/Zephyr-Core-3.5.0/boards/arm/stm32g081b_eval/
Dstm32g081b_eval.dts166 * to generate clock for delay counters and BMC Rx/Tx blocks. The rx is
197 * to generate clock for delay counters and BMC Rx/Tx blocks. The rx is
/Zephyr-Core-3.5.0/doc/services/device_mgmt/
Dmcumgr.rst427 consists basically of user-defined counters which are tightly connected to
437 variables (or counters), all with the same size (16, 32 or 64 bits).
454 The statistics counters can either have names or not, depending on the setting
485 Let's suppose we want to increment those counters by ``1``, ``2`` and ``3``
492 To get the current value of the counters in ``my_stats``::
/Zephyr-Core-3.5.0/drivers/pwm/
Dpwm_mcux_pwt.c155 /* Calculate sum of overflow counters */ in mcux_pwt_calc_period()
160 /* Calculate cycles from sum of overflow counters */ in mcux_pwt_calc_period()
/Zephyr-Core-3.5.0/drivers/dma/
Ddma_pl330.h47 /* Maximum possible values for PL330 ucode loop counters */
/Zephyr-Core-3.5.0/doc/connectivity/bluetooth/api/mesh/
Dsar_cfg.rst46 Intervals, timers and retransmission counters
78 behavior, such as intervals, timers and retransmission counters, over a mesh network using SAR argument
129 Four counters are related to SAR behavior:

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