| /Zephyr-latest/scripts/west_commands/runners/ |
| D | mdb.py | 37 # for simulation targets we start cores in direct order
45 # with secondary cores startup - so we reverse start order
46 return mdb_runner.cores - 1 - id
84 if mdb_runner.cores == 1:
87 elif 1 < mdb_runner.cores <= 12:
89 for i in range(mdb_runner.cores):
106 raise ValueError(f'unsupported cores {mdb_runner.cores}')
114 def __init__(self, cfg, cores=1, nsim_args=''): argument
117 self.cores = int(cores)
136 parser.add_argument('--cores', default=1,
[all …]
|
| /Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/ |
| D | Kconfig.soc | 20 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
27 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
35 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
42 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
50 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
58 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
66 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
|
| /Zephyr-latest/scripts/west_commands/tests/ |
| D | test_mdb.py | 33 'i': ['--cores=1', '--nsim_args=' + TEST_NSIM_ARGS],
42 'i': ['--cores=1', '--nsim_args=' + TEST_NSIM_ARGS],
50 TEST_NSIM_MULTICORE_CASES = [['--cores=2', '--nsim_args=' + TEST_NSIM_ARGS]]
64 'i': ['--jtag=digilent', '--cores=1'],
70 'i': ['--jtag=digilent', '--cores=1', '--dig-device=test'],
79 'i': ['--jtag=digilent', '--cores=1'],
84 'i': ['--jtag=digilent', '--cores=1', '--dig-device=test'],
92 'i': ['--jtag=test_debug', '--cores=1'],
95 'i': ['--jtag=digilent', '--cores=13'],
96 'e': "unsupported cores 13"
[all …]
|
| /Zephyr-latest/boards/nxp/ls1046ardb/ |
| D | ls1046ardb_ls1046a_smp_4cores.yaml | 1 identifier: ls1046ardb/ls1046a/smp/4cores
2 name: NXP LS1046ARDB SMP on four CPU Cores
|
| /Zephyr-latest/boards/snps/hsdk/ |
| D | hsdk_arc_hsdk_2cores.yaml | 1 identifier: hsdk/arc_hsdk/2cores
2 name: HS Development Kit(2 cores)
|
| D | board.cmake | 5 board_runner_args(openocd "--config=${CMAKE_CURRENT_LIST_DIR}/support/openocd-2-cores.cfg")
8 board_runner_args(mdb-hw "--jtag=digilent" "--cores=${CONFIG_MP_MAX_NUM_CPUS}")
|
| /Zephyr-latest/tests/benchmarks/latency_measure/boards/ |
| D | intel_adsp_ace15_mtpm_sim.conf | 1 # Due to addition of busy threads running on other cores,
3 # all cores, we are wasting quite a bit of time just busy
|
| D | intel_adsp_ace20_lnl_sim.conf | 1 # Due to addition of busy threads running on other cores,
3 # all cores, we are wasting quite a bit of time just busy
|
| D | intel_adsp_ace30_ptl_sim.conf | 1 # Due to addition of busy threads running on other cores,
3 # all cores, we are wasting quite a bit of time just busy
|
| /Zephyr-latest/tests/benchmarks/sched/boards/ |
| D | intel_adsp_ace15_mtpm_sim.conf | 1 # Due to addition of busy threads running on other cores,
3 # all cores, we are wasting quite a bit of time just busy
|
| D | intel_adsp_ace20_lnl_sim.conf | 1 # Due to addition of busy threads running on other cores,
3 # all cores, we are wasting quite a bit of time just busy
|
| D | intel_adsp_ace30_ptl_sim.conf | 1 # Due to addition of busy threads running on other cores,
3 # all cores, we are wasting quite a bit of time just busy
|
| /Zephyr-latest/boards/snps/nsim/arc_classic/ |
| D | nsim_nsim_hs5x_smp_12cores.yaml | 1 identifier: nsim/nsim_hs5x/smp/12cores
2 name: Multi-core HS5x nSIM simulator (12 cores)
|
| D | nsim_nsim_hs6x_smp_12cores.yaml | 1 identifier: nsim/nsim_hs6x/smp/12cores
2 name: Multi-core HS6x nSIM simulator (12 cores)
|
| D | board.yml | 20 - name: 12cores
25 - name: 12cores
|
| D | board.cmake | 17 board_runner_args(mdb-nsim "--cores=${CONFIG_MP_MAX_NUM_CPUS}" "--nsim_args=${MDB_ARGS}")
18 board_runner_args(mdb-hw "--cores=${CONFIG_MP_MAX_NUM_CPUS}")
|
| /Zephyr-latest/tests/kernel/spinlock/src/ |
| D | spinlock_fairness.c | 43 /* Synchronize all the cores as much as possible */ in test_thread()
51 * Run the test: let the cores contend for the spinlock and in test_thread()
97 * other cores - the less chances to win a contention for the spinlock in test_init()
109 * to the cores contending for the spinlock. Memory access latency may
110 * vary between the CPU cores, so that some CPUs reach the spinlock faster
113 * cores, making them to starve.
118 * spinlock is evenly distributed between all of the contending cores.
|
| /Zephyr-latest/doc/kernel/object_cores/ |
| D | index.rst | 3 Object Cores
6 Object cores are a kernel debugging tool that can be used to both identify and
18 cores to form a singly linked list. Each object core also links to the their
20 linking together all the object cores of that type. Object types are also
24 Object cores have been integrated into following kernel objects:
44 Object cores provide a uniform means to retrieve that information via object
76 initialized for use with object cores and object core statistics.
120 automatically have their object cores initialized when the object is
136 Walking a List of Object Cores
139 Two routines exist for walking the list of object cores linked to an object
|
| /Zephyr-latest/samples/arch/smp/pi/ |
| D | README.rst | 9 demonstrates the benefit of multiple execution units (CPU cores)
14 can see that using more cores takes almost linearly less time
46 All 16 threads executed by 4 cores in 28 msec
|
| /Zephyr-latest/boards/raspberrypi/rpi_pico2/ |
| D | rpi_pico2_rp2350a_m33.dts | 19 /* there's nothing specific to the Cortex-M33 cores vs the (not yet
20 * implemented) Hazard3 cores.
|
| /Zephyr-latest/doc/kernel/data_structures/ |
| D | mpsc_lockfree.rst | 8 at `1024cores <https://www.1024cores.net/home/lock-free-algorithms/queues/intrusive-mpsc-node-based…
|
| /Zephyr-latest/boards/intel/rpl/doc/ |
| D | index.rst | 10 architecture, utilizing P-cores for performance and E-Cores for efficiency.
21 For more information about Raptor Lake Processor lines, P-cores, and E-cores
|
| /Zephyr-latest/doc/services/llext/ |
| D | index.rst | 24 available only on RISC-V, ARM, ARM64, ARC (experimental) and Xtensa cores.
25 Harvard architecture cores that separate code and data paths and have no
|
| /Zephyr-latest/arch/arm64/ |
| D | Kconfig | 23 A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...)
25 option must be selected when such cores are connected to an interrupt
|
| /Zephyr-latest/arch/arc/core/ |
| D | smp.c | 28 * arc_cpu_wake_flag is used to sync up master core and slave cores
79 /* Debugger halts cores at all conditions: in arc_connect_debug_mask_update()
93 /* the C entry of slave cores */
145 /* Send sched_ipi request to other cores in arch_sched_directed_ipi()
193 /* when all cores halt, gfrc halt */ in arch_smp_init()
|
