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/Zephyr-latest/.github/workflows/
Dcodecov.yaml1 name: Code Coverage with codecov
5 - cron: '25 06,18 * * *'
8 group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }}
9 cancel-in-progress: true
12 codecov:
13 if: github.repository_owner == 'zephyrproject-rtos'
14 runs-on:
15 group: zephyr-runner-v2-linux-x64-4xlarge
17 image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026
18 options: '--entrypoint /bin/bash'
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/Zephyr-latest/scripts/ci/
Dcheck_compliance.py5 # SPDX-License-Identifier: Apache-2.0
57 f"{cp.stdout.decode('utf-8')}\n"
59 f"{cp.stderr.decode('utf-8')}\n")
61 return cp.stdout.decode("utf-8").rstrip()
70 return git('rev-list',
71 f'--max-count={-1 if "." in refspec else 1}', refspec).split()
74 filter_arg = (f'--diff-filter={filter}',) if filter else ()
75 paths_arg = ('--', *paths) if paths else ()
76 out = git('diff', '--name-only', *filter_arg, COMMIT_RANGE, *paths_arg)
128 - The magic string "<zephyr-base>" can be used to refer to the
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/Zephyr-latest/doc/releases/
Drelease-notes-2.1.rst13 * Expanded support for ARMv6-M architecture.
50 hardware-based stack overflow detection) in ARMv6-M architecture
51 * Added QEMU support for ARMv6-M architecture
52 * Extended test coverage for ARM-specific kernel features in ARMv6-M
54 * Enhanced runtime MPU programming in ARMv8-M architecture, making
55 the full partitioning of kernel SRAM memory a user-configurable
57 * Added CMSIS support for Cortex-R architectures.
59 * Added missing Cortex-R CPU device tree bindings.
60 * Fixed incorrect Cortex-R device tree specification.
68 * RISC-V:
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