| /Zephyr-Core-3.5.0/samples/boards/ti/cc13x2_cc26x2/system_off/src/ |
| D | ext_flash.c | 5 * SPDX-License-Identifier: Apache-2.0
29 /* SPI Flash CS */ in CC1352R1_LAUNCHXL_sendExtFlashByte()
33 gpio_pin_set(dev, DIO10_PIN, 0); /* SPI Flash CLK */ in CC1352R1_LAUNCHXL_sendExtFlashByte()
36 gpio_pin_set(dev, DIO9_PIN, (byte >> (7 - i)) & 0x01); in CC1352R1_LAUNCHXL_sendExtFlashByte()
37 gpio_pin_set(dev, DIO10_PIN, 1); /* SPI Flash CLK */ in CC1352R1_LAUNCHXL_sendExtFlashByte()
40 * Waste a few cycles to keep the CLK high for at in CC1352R1_LAUNCHXL_sendExtFlashByte()
47 gpio_pin_set(dev, DIO10_PIN, 0); /* CLK */ in CC1352R1_LAUNCHXL_sendExtFlashByte()
48 gpio_pin_set(dev, DIO20_PIN, 1); /* CS */ in CC1352R1_LAUNCHXL_sendExtFlashByte()
51 * Keep CS high at least 40 us in CC1352R1_LAUNCHXL_sendExtFlashByte()
87 printk("%s: device not ready.\n", dev->name); in CC1352R1_LAUNCHXL_shutDownExtFlash()
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| /Zephyr-Core-3.5.0/dts/bindings/spi/ |
| D | espressif,esp32-spi.yaml | 3 compatible: "espressif,esp32-spi"
5 include: [spi-controller.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 half-duplex:
20 Enable half-duplex communication mode.
24 dummy-comp:
31 Enable 3-wire mode
35 dma-enabled:
39 dma-clk:
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/google_dragonclaw/doc/ |
| D | index.rst | 9 Dragonclaw is a board created by Google for fingerprint-related functionality
19 - STM32F412CGU6 UFQFPN48 package
24 - USART_1 TX/RX : PA9/PA10
25 - USART_2 TX/RX : PA2/PA3
26 - SPI_1 CS/CLK/MISO/MOSI : PA4/PA5/PA6/PA7
27 - SPI_2 CS/CLK/MISO/MOSI : PB12/PB13/PB14/PB15
32 Build application as usual for the ``dragonclaw`` board, and flash
33 using μServo or an external J-Link connected to J4. If μServo is used, please
39 Use SWD with a J-Link or ST-Link. Remember that SW2 must be set to CORESIGHT.
44 .. target-notes::
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| /Zephyr-Core-3.5.0/drivers/fpga/ |
| D | fpga_ice40.c | 4 * SPDX-License-Identifier: Apache-2.0
24 * Note: When loading a bitstream, the iCE40 has a 'quirk' in that the CS
27 * CS polarity is normal (active low). Zephyr's SPI driver model currently
30 * The logical alternative would be to put the CS into GPIO mode, perform 3
31 * separate SPI transfers (inverting CS polarity as necessary) and then
32 * restore the default pinctrl settings. On some higher-end microcontrollers
36 * However, on lower-end microcontrollers, the amount of time that elapses
38 * leaves us with the bitbanging option. Of course, on lower-end
42 * in order to bitbang on lower-end microcontrollers, we actually require
47 * - FPGA_ICE40_LOAD_MODE_SPI (for higher-end microcontrollers)
[all …]
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| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | ti,boosterpack-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 GPIO pins exposed as BoosterPack headers on TI LaunchPads.
9 BoosterPack plug-in modules are available in 20 and 40 pin variants. The
18 2 Analog 22 GND 39 GPIO 19 GPIO / SPI CS
23 7 SPI CLK 27 Analog 34 GPIO 14 SPI MISO
24 8 GPIO 28 Analog 33 GPIO 13 GPIO / SPI CS
25 9 I2C SCL 29 32 GPIO 12 GPIO / SPI CS
32 compatible: "ti,boosterpack-header"
34 include: [gpio-nexus.yaml, base.yaml]
|
| /Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/common/ |
| D | Kconfig.soc | 2 # SPDX-License-Identifier: Apache-2.0
16 bool "Support for external, SPI-connected RAM"
66 bool "ESP-PSRAM16 or APS1604"
69 bool "ESP-PSRAM32 or IS25WP032"
72 bool "ESP-PSRAM64 or LY68L6400"
124 menu "PSRAM clock and cs IO for ESP32-DOWD"
127 int "PSRAM CLK IO number"
135 int "PSRAM CS IO number"
139 The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
142 endmenu # PSRAM clock and cs IO for ESP32-DOWD
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| /Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/esp32s2/ |
| D | Kconfig.soc | 2 # SPDX-License-Identifier: Apache-2.0
7 bool "ESP32S2 as target SOC"
15 prompt "ESP32-S2 SOC Selection"
63 Choose which clock is used as RTC clock source.
65 - "Internal 90kHz oscillator" option provides lowest deep sleep current
69 - "External 32kHz crystal" provides better frequency stability, at the
71 - "External 32kHz oscillator" allows using 32kHz clock generated by an
77 ground. 32K_XP pin can not be used as a GPIO in this case.
78 - "Internal 8MHz oscillator divided by 256" option results in higher
114 - 90000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/nxp/ |
| D | nxp_rt6xx_common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,cortex-m33f";
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| /Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/esp32s3/ |
| D | Kconfig.soc | 2 # SPDX-License-Identifier: Apache-2.0
7 bool "ESP32S3 as target SOC"
15 prompt "ESP32-S3 SOC Selection"
68 Choose which clock is used as RTC clock source.
99 - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
100 - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
118 When using the default (Espressif-assigned) base MAC address, either setting can be used.
297 bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled"
301 If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered
307 menu "PSRAM Clock and CS IO for ESP32S3"
[all …]
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| /Zephyr-Core-3.5.0/drivers/spi/ |
| D | spi_numaker.c | 2 * SPDX-License-Identifier: Apache-2.0
41 * CPOL/CPHA = 0/0 --> SPI_MODE_0
42 * CPOL/CPHA = 0/1 --> SPI_MODE_1
43 * CPOL/CPHA = 1/0 --> SPI_MODE_2
44 * CPOL/CPHA = 1/1 --> SPI_MODE_3
57 struct spi_numaker_data *data = dev->data; in spi_numaker_configure()
58 const struct spi_numaker_config *dev_cfg = dev->config; in spi_numaker_configure()
61 if (spi_context_configured(&data->ctx, config)) { in spi_numaker_configure()
65 if (SPI_MODE_GET(config->operation) & SPI_MODE_LOOP) { in spi_numaker_configure()
67 return -ENOTSUP; in spi_numaker_configure()
[all …]
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| D | spi_xec_qmspi_ldma.c | 4 * SPDX-License-Identifier: Apache-2.0
19 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
20 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
34 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
35 * to sample input line(s) on same edge as output data is ready.
122 return -ETIMEDOUT; in xec_qmspi_spin_yield()
132 * Some QMSPI timing register may be modified by the Boot-ROM OTP
143 taps[0] = regs->TM_TAPS; in qmspi_reset()
144 taps[1] = regs->TM_TAPS_ADJ; in qmspi_reset()
145 taps[2] = regs->TM_TAPS_CTRL; in qmspi_reset()
[all …]
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| /Zephyr-Core-3.5.0/drivers/espi/ |
| D | espi_saf_mchp_xec_v2.c | 5 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
27 /* SAF EC Portal read/write flash access limited to 1-64 bytes */
61 * Delay before first Poll-1 command after suspend in 20 ns units
96 static inline void mchp_saf_cs_descr_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_cs_descr_wr() argument
99 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
102 static inline void mchp_saf_poll2_mask_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_poll2_mask_wr() argument
105 LOG_DBG("%s cs: %d mask %x", __func__, cs, val); in mchp_saf_poll2_mask_wr()
106 if (cs == 0) { in mchp_saf_poll2_mask_wr()
107 regs->SAF_CS0_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
[all …]
|
| /Zephyr-Core-3.5.0/soc/arm/nxp_imx/rt/ |
| D | flexspi_nor_config.h | 6 * SPDX-License-Identifier: Apache-2.0
186 /* !< Switch to 0-4-4/0-8-8 mode */
199 /* !< [0x000-0x003] Tag, fixed value 0x42464346UL */
201 /* !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */
203 /* !< [0x008-0x00b] Reserved for future use */
205 /* !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */
207 /* !< [0x00d-0x00d] CS hold time, default value: 3 */
209 /* !< [0x00e-0x00e] CS setup time, default value: 3 */
211 /* !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For */
214 /* !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */
[all …]
|
| /Zephyr-Core-3.5.0/samples/sensor/bme280/ |
| D | README.rst | 13 https://www.bosch-sensortec.com/products/environmental-sensors/humidity-sensors-bme280/
23 or SPI. Configuration is done via :ref:`devicetree <dt-guide>`. The devicetree
33 https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bme280-ds002.pdf
35 Boards with a built-in BME280
41 .. zephyr-app-commands::
42 :zephyr-app: samples/sensor/bme280
52 .. zephyr-app-commands::
53 :zephyr-app: samples/sensor/bme280
55 :gen-args: -DDTC_OVERLAY_FILE=arduino_spi.overlay
58 works on any board with a properly configured Arduino pin-compatible SPI
[all …]
|
| /Zephyr-Core-3.5.0/boards/arm/cc1352p1_launchxl/doc/ |
| D | index.rst | 9 The Texas Instruments CC1352P LaunchPad |trade| (LAUNCHXL-CC1352P1) is a
10 development kit for the SimpleLink |trade| multi-Standard CC1352P wireless MCU.
29 The CC1352P wireless MCU has a 48 MHz Arm |reg| Cortex |reg|-M4F SoC and an
30 integrated sub-1GHz and 2.4 GHz transceiver with integrated 20dBm power amplifier
42 +-----------+------------+----------------------+
45 | GPIO | on-chip | gpio |
46 +-----------+------------+----------------------+
47 | MPU | on-chip | arch/arm |
48 +-----------+------------+----------------------+
49 | NVIC | on-chip | arch/arm |
[all …]
|
| /Zephyr-Core-3.5.0/boards/arm/cc26x2r1_launchxl/doc/ |
| D | index.rst | 9 The Texas Instruments CC26x2R LaunchPad |trade| (LAUNCHXL-CC26X2R1) is a
10 development kit for the SimpleLink |trade| multi-Standard CC2652R wireless MCU.
27 The CC2652 wireless MCU has a 48 MHz Arm |reg| Cortex |reg|-M4F SoC and an
39 +-----------+------------+----------------------+
42 | GPIO | on-chip | gpio |
43 +-----------+------------+----------------------+
44 | MPU | on-chip | arch/arm |
45 +-----------+------------+----------------------+
46 | NVIC | on-chip | arch/arm |
47 +-----------+------------+----------------------+
[all …]
|
| /Zephyr-Core-3.5.0/boards/arm/cc1352r1_launchxl/doc/ |
| D | index.rst | 9 The Texas Instruments CC1352R LaunchPad |trade| (LAUNCHXL-CC1352R1) is a
10 development kit for the SimpleLink |trade| multi-Standard CC1352R wireless MCU.
27 The CC13522 wireless MCU has a 48 MHz Arm |reg| Cortex |reg|-M4F SoC and an
28 integrated Sub-1 and 2.4 GHz transceiver supporting multiple protocols including
39 +-----------+------------+----------------------+
42 | GPIO | on-chip | gpio |
43 +-----------+------------+----------------------+
44 | MPU | on-chip | arch/arm |
45 +-----------+------------+----------------------+
46 | NVIC | on-chip | arch/arm |
[all …]
|
| /Zephyr-Core-3.5.0/boards/arm/cc1352r_sensortag/doc/ |
| D | index.rst | 9 The Texas Instruments CC1352R SensorTag |trade| (LPSTK-CC1352R) is a
10 development kit for the SimpleLink |trade| multi-Standard CC1352R wireless MCU.
27 The CC13522 wireless MCU has a 48 MHz Arm |reg| Cortex |reg|-M4F SoC and an
28 integrated Sub-1 and 2.4 GHz transceiver supporting multiple protocols including
39 +-----------+------------+------------------+
42 | GPIO | on-chip | gpio |
43 +-----------+------------+------------------+
44 | MPU | on-chip | arch/arm |
45 +-----------+------------+------------------+
46 | NVIC | on-chip | arch/arm |
[all …]
|
| /Zephyr-Core-3.5.0/boards/arm/mec172xmodular_assy6930/doc/ |
| D | mec172xmodular_assy6930.rst | 22 - MEC172x (MEC1723, MEC1727 and MEC1728) ARM Cortex-M4 Processor
23 - 416 KB RAM and 128 KB boot ROM
24 - UART1 using microUSB
25 - PECI interface 3.0
26 - FAN, PWM and TACHO pins
27 - 5 SMBus instances
28 - eSPI header
29 - VCI interface
30 - 1 hardware driven PS/2 ports
31 - Keyboard interface headers
[all …]
|
| /Zephyr-Core-3.5.0/boards/xtensa/esp_wrover_kit/doc/ |
| D | index.rst | 3 ESP-WROVER-KIT
9 ESP-WROVER-KIT is an ESP32-based development board produced by `Espressif <https://www.espressif.co…
11 ESP-WROVER-KIT features the following integrated components:
13 - ESP32-WROVER-E module
14 - LCD screen
15 - MicroSD card slot
17 Its another distinguishing feature is the embedded FTDI FT2232HL chip - an advanced multi-interface
19 without a separate JTAG debugger. ESP-WROVER-KIT makes development convenient, easy, and
20 cost-effective.
26 … ESP32's GPIO16 and GPIO17 are used as chip select and clock signals for PSRAM. By default, the two
[all …]
|
| /Zephyr-Core-3.5.0/boards/arm/bt610/doc/ |
| D | bt610.rst | 11 Cortex-M4F CPU.
19 * :abbr:`I2C (Inter-Integrated Circuit)`
28 * :abbr:`UART (Universal Asynchronous Receiver-Transmitter)`
55 +-----------+------------+----------------------+
58 | ADC | on-chip | adc |
59 +-----------+------------+----------------------+
60 | CLOCK | on-chip | clock_control |
61 +-----------+------------+----------------------+
62 | FLASH | on-chip | flash |
63 +-----------+------------+----------------------+
[all …]
|
| /Zephyr-Core-3.5.0/boards/arm/mec15xxevb_assy6853/doc/ |
| D | index.rst | 13 MEC150x except for an enhanced Boot-ROM SPI loader. The SPI image format has
25 - MEC1521HA0SZ ARM Cortex-M4 Processor
26 - 256 KB RAM and 64 KB boot ROM
27 - Keyboard interface
28 - ADC & GPIO headers
29 - UART0, UART1, and UART2
30 - FAN0, FAN1, FAN2 headers
31 - FAN PWM interface
32 - JTAG/SWD, ETM and MCHP Trace ports
33 - PECI interface 3.0
[all …]
|
| /Zephyr-Core-3.5.0/doc/releases/ |
| D | release-notes-3.5.rst | 20 * Bluetooth: improvements to the Controller, Audio, Mesh, as well as the host stack in
38 * CVE-2023-3725 `Zephyr project bug tracker GHSA-2g3m-p6c7-8rr3
39 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-2g3m-p6c7-8rr3>`_
41 * CVE-2023-4257 `Zephyr project bug tracker GHSA-853q-q69w-gf5j
42 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-853q-q69w-gf5j>`_
44 * CVE-2023-4258 `Zephyr project bug tracker GHSA-m34c-cp63-rwh7
45 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-m34c-cp63-rwh7>`_
47 * CVE-2023-4259 `Zephyr project bug tracker GHSA-gghm-c696-f4j4
48 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gghm-c696-f4j4>`_
50 * CVE-2023-4260 `Zephyr project bug tracker GHSA-gj27-862r-55wh
[all …]
|
| D | release-notes-3.2.rst | 13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
155 * ``label`` property from devicetree as a base property. The property is still
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/mec172xevb_assy6906/doc/ |
| D | index.rst | 21 - MEC172x ARM Cortex-M4 Processor
22 - 416 KB RAM and 128 KB boot ROM
23 - Keyboard interface
24 - ADC & GPIO headers
25 - UART0 and UART1
26 - FAN0, FAN1, FAN2 headers
27 - FAN PWM interface
28 - JTAG/SWD, ETM and MCHP Trace ports
29 - PECI interface 3.0
30 - I2C voltage translator
[all …]
|
