| /Zephyr-latest/soc/espressif/common/ |
| D | Kconfig.flash | 18 Enable this to support auto detection of ISSI chips if chip vendor not directly
19 given by ``chip_drv`` member of the chip struct. This adds support for variant
26 Enable this to support auto detection of MXIC chips if chip vendor not directly
27 given by ``chip_drv`` member of the chip struct. This adds support for variant
34 Enable this to support auto detection of GD (GigaDevice) chips if chip vendor not
35 directly given by ``chip_drv`` member of the chip struct. If you are using Wrover
40 size. Note that the default chip driver supports the GD chips with product ID
47 Enable this to support auto detection of Winbond chips if chip vendor not directly
48 given by ``chip_drv`` member of the chip struct. This adds support for variant
55 Enable this to support auto detection of BOYA chips if chip vendor not directly
[all …]
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| /Zephyr-latest/tests/kernel/device/src/ |
| D | mmio_multireg.c | 20 DEVICE_MMIO_NAMED_RAM(chip);
27 DEVICE_MMIO_NAMED_ROM(chip);
32 DEVICE_MMIO_NAMED_ROM_INIT_BY_NAME(chip, DT_DRV_INST(0)),
41 DEVICE_MMIO_NAMED_MAP(dev, chip, K_MEM_CACHE_NONE); in foo_multireg_init()
69 regs_chip = DEVICE_MMIO_NAMED_GET(dev, chip); in ZTEST()
71 rom_chip = DEVICE_MMIO_NAMED_ROM_PTR(dev, chip); in ZTEST()
78 zassert_equal(rom_chip->phys_addr, DT_INST_REG_ADDR_BY_NAME(0, chip), in ZTEST()
79 "bad phys_addr (chip)"); in ZTEST()
80 zassert_equal(rom_chip->size, DT_INST_REG_SIZE_BY_NAME(0, chip), in ZTEST()
81 "bad size (chip)"); in ZTEST()
[all …]
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| /Zephyr-latest/scripts/west_commands/runners/ |
| D | probe_rs.py | 12 def __init__(self, cfg, chip, argument
22 self.args = ['--chip', chip]
45 parser.add_argument('--chip', required=True,
46 help='chip name')
57 e.g. --chip-description-path=/path/to/chip.yml'''
61 return ProbeRsBinaryRunner(cfg, args.chip,
75 download_args += ['--chip-erase']
|
| /Zephyr-latest/dts/bindings/mtd/ |
| D | atmel,at45.yaml | 36 Value of zero means that the flash chip has all sectors of equal size.
48 no-chip-erase:
51 If set, indicates that the chip does not support the chip erase command.
56 If set, indicates that the chip does not support the sector erase command.
62 of the default Deep Power-Down one to put the chip into low power mode.
65 SRAM buffers in the chip, the difference between the Deep and Ultra-Deep
66 Power-Down modes is that the chip consumes far less power in the latter
73 Time, in nanoseconds, needed by the chip to enter the Deep Power-Down
81 Time, in nanoseconds, needed by the chip to exit from the Deep Power-Down
|
| D | ti,cc23x0-ccfg-flash.yaml | 76 commands are always allowed after a chip erase and until the first reset after the CCFG
83 Reset to allowed after a chip erase.
85 ti,chip-erase:
88 Determines whether chip erasing SACI commands are allowed.
141 ti,chip-er-retain-sect0-31:
144 Bitmask for chip erase protection of individual sectors in sector range [0, 31].
145 Controls whether a chip erase affects a sector or not. The mechanism is intended
147 the chip erase during a FW update.
153 ti,chip-er-retain-sect32-255:
156 Bitmask for chip erase protection of groups of 8 sectors, in sector range [32, 255].
|
| /Zephyr-latest/boards/96boards/carbon/doc/ |
| D | nrf51822.rst | 9 This is the secondary nRF51822 chip on the 96Boards Carbon and provides
10 Bluetooth functionality to the main STM32F401RET chip via SPI.
16 unless they want to reprogram the secondary chip which provides
29 different chip.
37 | NVIC | on-chip | nested vector interrupt controller |
39 | RTC | on-chip | system clock |
41 | UART | on-chip | serial port |
43 | GPIO | on-chip | gpio |
45 | FLASH | on-chip | flash |
47 | SPIS | on-chip | SPI slave |
[all …]
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| /Zephyr-latest/soc/nuvoton/npcm/common/esiost/ |
| D | esiost_args.py | 63 """populate the chip related fields for the esiost"""
65 chip = str(self.chip_name).lower()
67 if chip not in CHIPS_INFO:
71 self.chip_ram_address = CHIPS_INFO[chip]['ram_address']
72 self.chip_ram_size = CHIPS_INFO[chip]['ram_size']
87 elif (arg == "chip") & (argument_list.chip is not None):
88 self.chip_name = argument_list.chip
104 parser.add_argument("-chip", dest="chip")
|
| /Zephyr-latest/soc/raspberrypi/rpi_pico/rp2040/ |
| D | Kconfig | 30 Configure RP2 to use a W25Q080 flash chip, or similar. Should be selected
36 Configure RP2 to use a flash chip supporting the standard 03h command.
42 Configure RP2 to use a IS25LP080 flash chip, or similar. Should be selected
48 Configure RP2 to use a W25X10CL flash chip, or similar. Should be selected
54 Configure RP2 to use a AT25SF128A flash chip, or similar. Should be selected
|
| /Zephyr-latest/drivers/gpio/ |
| D | Kconfig.mcp23xxx | 13 bool "MCP230XX I2C-based GPIO chip"
23 Enable driver for MCP230XX I2C-based GPIO chip.
36 bool "MCP23SXX SPI-based GPIO chip"
45 Enable driver for MCP23SXX SPI-based GPIO chip.
|
| D | Kconfig.rt1718s | 7 bool "RT1718S I2C-based TCPC chip with GPIOs"
11 Enable driver GPIO for RT1718S I2C-based TCPC chip.
33 from the chip.
|
| /Zephyr-latest/dts/bindings/spi/ |
| D | intel,penwell-spi.yaml | 22 Chip select configuration. possible values:
31 Use GSPI chip select CS0 or CS1. GSPI 0, 1 & 2 instance supports both chip selects.
33 Chip select output possible values:
|
| D | nxp,lpc-spi.yaml | 14 Delay in nanoseconds inserted between chip select assert to the first
20 Delay in nanoseconds inserted between the last clock edge to the chip
26 Delay in nanoseconds inserted between data frames when chip select is
33 Delay in nanoseconds inserted between transfers when chip select is
|
| D | microchip,xec-qmspi-ldma.yaml | 48 chip-select:
51 Use QMSPI CS0# or CS1#. Port 0 supports both chip selects.
58 If not present use hardware default value. Refer to chip documentation
65 If not present use hardware default value. Refer to chip documentation
72 and WP#. If not present use hardware default value. Refer to chip
79 If not present use hardware default value. Refer to chip documentation
|
| D | nxp,s32-spi.yaml | 21 The number of the Chip Select signals.
41 deactivating Chip Select at the stop of transfer. If CS remains
50 A delay in nanoseconds between activating Chip Select and the start
60 A delay in nanoseconds between deactivating Chip Select at the stop
61 of previous transfer and activating Chip Select at the start of
|
| /Zephyr-latest/dts/bindings/gpio/ |
| D | richtek,rt1718s.yaml | 5 Richtek RT1718S TCPC chip
7 The Richtek RT1718S chip is TCPC, but also has 3 pins, which can be used as
8 a usual GPIO. This node collects common properties for RT1718S chip e.g. I2C
36 description: Interrupt GPIO pin connected from the chip(IRQB)
|
| /Zephyr-latest/include/zephyr/devicetree/ |
| D | spi.h | 26 * @brief Does a SPI controller node have chip select GPIOs configured?
29 * chip select GPIOs. Its value is a phandle-array which specifies the
30 * chip select lines.
55 * @brief Number of chip select GPIOs in a SPI controller's cs-gpios property
83 * @brief Does a SPI device have a chip select line configured?
114 * @return 1 if spi_dev's bus node DT_BUS(spi_dev) has a chip select
120 * @brief Get a SPI device's chip select GPIO controller's node identifier
148 * @return node identifier for spi_dev's chip select GPIO controller
154 * @brief Get a SPI device's chip select GPIO pin number
181 * @return pin number of spi_dev's chip select GPIO
[all …]
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| /Zephyr-latest/boards/nxp/frdm_rw612/doc/ |
| D | index.rst | 11 The RW612 MCU subsystem includes 1.2 MB of on-chip SRAM and a high-bandwidth Quad SPI interface
12 with an on-the-fly decryption engine for securely accessing off-chip XIP flash.
21 - 1.2 MB on-chip SRAM
29 | NVIC | on-chip | nested vector interrupt controller|
31 | SYSTICK | on-chip | systick |
33 | MCI_IOMUX | on-chip | pinmux |
35 | GPIO | on-chip | gpio |
37 | USART | on-chip | serial |
39 | DMA | on-chip | dma |
41 | SPI | on-chip | spi |
[all …]
|
| /Zephyr-latest/boards/nxp/rd_rw612_bga/doc/ |
| D | index.rst | 11 The RW612 MCU subsystem includes 1.2 MB of on-chip SRAM and a high-bandwidth Quad SPI interface
12 with an on-the-fly decryption engine for securely accessing off-chip XIP flash.
21 - 1.2 MB on-chip SRAM
29 | NVIC | on-chip | nested vector interrupt controller|
31 | SYSTICK | on-chip | systick |
33 | MCI_IOMUX | on-chip | pinmux |
35 | GPIO | on-chip | gpio |
37 | USART | on-chip | serial |
39 | DMA | on-chip | dma |
41 | SPI | on-chip | spi |
[all …]
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| /Zephyr-latest/boards/sensry/ganymed_bob/doc/ |
| D | index.rst | 76 | SAADC | on-chip | adc |
78 | CLOCK | on-chip | clock_control |
80 | MRAM | on-chip | flash |
82 | GPIO | on-chip | gpio |
84 | TWIM | on-chip | i2c |
86 | PWM | on-chip | pwm |
88 | GRTC | on-chip | counter |
92 | SPI(M/S) | on-chip | spi |
94 | SPU | on-chip | system protection |
96 | UART | on-chip | serial |
[all …]
|
| /Zephyr-latest/boards/lowrisc/opentitan_earlgrey/doc/ |
| D | index.rst | 6 The OpenTitan Earl Grey chip is a low-power secure microcontroller that is
9 chip.
24 Detailed specification is on the `OpenTitan Earl Grey Chip Datasheet`_.
30 the Earl Grey chip simulated in Verilator, a cycle-accurate HDL simulation tool.
35 | NVIC | on-chip | nested vector interrupt controller |
37 | Timer | on-chip | RISC-V Machine Timer |
39 | UART | on-chip | serial port-polling |
41 | SPI | on-chip | SPI host |
43 | WDT | on-chip | Always-On Timer (Watchdog) |
91 .. _OpenTitan Earl Grey Chip Datasheet: https://opentitan.org/book/hw/top_earlgrey/doc/specificatio…
|
| /Zephyr-latest/dts/bindings/w1/ |
| D | maxim,ds2477_85_common.yaml | 24 off: off (chip reset value)
43 off: off (chip reset value)
62 "extern" (chip reset value)
78 150 (default; chip reset value)
90 50 (default; chip reset value)
|
| /Zephyr-latest/drivers/clock_control/ |
| D | Kconfig.npcx | 16 bool "Generate LFCLK by on-chip Crystal Oscillator"
19 is generated by the on-chip Crystal Oscillator (XTOSC).
20 This includes an on-chip oscillator, to which an external crystal
|
| /Zephyr-latest/boards/norik/octopus_som/doc/ |
| D | index.rst | 41 | ADC | on-chip | adc |
43 | CLOCK | on-chip | clock_control |
45 | FLASH | on-chip | flash |
47 | GPIO | on-chip | gpio |
49 | I2C(M) | on-chip | i2c |
51 | MPU | on-chip | arch/arm |
53 | NVIC | on-chip | arch/arm |
55 | PWM | on-chip | pwm |
57 | RTC | on-chip | system clock |
61 | SPI(M/S) | on-chip | spi |
[all …]
|
| /Zephyr-latest/include/zephyr/drivers/mfd/ |
| D | ad559x.h | 40 * @brief Check if the chip has a pointer byte map
44 * @retval true if chip has a pointer byte map, false if it has normal register map
49 * @brief Read raw data from the chip
61 * @brief Write raw data to chip
98 * @brief Read ADC channel data from the chip
110 * @brief Write ADC channel data to the chip
122 * @brief Read GPIO port from the chip
|
| /Zephyr-latest/boards/nxp/rddrone_fmuk66/doc/ |
| D | index.rst | 44 | NVIC | on-chip | nested vector interrupt controller |
46 | SYSTICK | on-chip | systick |
48 | PINMUX | on-chip | pinmux |
50 | GPIO | on-chip | gpio |
52 | I2C | on-chip | i2c |
54 | SPI | on-chip | spi |
56 | WATCHDOG | on-chip | watchdog |
58 | ADC | on-chip | adc |
60 | DAC | on-chip | dac |
62 | PWM | on-chip | pwm |
[all …]
|
