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/Zephyr-latest/dts/bindings/gpio/
Dxlnx,ps-gpio.yaml18 Zynq-7000 (comp. Zynq-7000 TRM, chap. 14.1.2, p. 381):
24 ZynqMP (UltraScale) (comp. Ultrascale TRM, chap. 27, p. 769):
/Zephyr-latest/include/zephyr/arch/arm/mmu/
Darm_mmu.h18 * Table B3-10, chap. B3.8.2, p. B3-1363f.
20 * Table B3-11, chap. B3.8.2, p. B3-1364
/Zephyr-latest/arch/arm/core/cortex_a_r/
Dprep_c.c49 * chap. B4.1.40 in z_arm_floating_point_init()
68 * chap. B6.1.38 in z_arm_floating_point_init()
/Zephyr-latest/drivers/gpio/
Dgpio_xlnx_ps_bank.h15 * Register address offsets: comp. Zynq-7000 TRM, ug585, chap. B.19
/Zephyr-latest/subsys/net/l2/ppp/
Dmisc.c196 return "CHAP"; in ppp_proto2str()
/Zephyr-latest/modules/hostap/
DCMakeLists.txt446 zephyr_library_sources(${HOSTAP_SRC_BASE}/eap_common/chap.c)
/Zephyr-latest/arch/arm/core/mmu/
Darm_mmu.c281 * TEX, C, B, S: Table B3-10, chap. B3.8.2, p. B3-1363f. in arm_mmu_convert_attr_flags()
282 * AP : Table B3-6, chap. B3.7.1, p. B3-1353. in arm_mmu_convert_attr_flags()
/Zephyr-latest/drivers/serial/
Duart_xlnx_ps.c42 * Comp. Xilinx Zynq-7000 Technical Reference Manual (ug585), chap. B.33