| /Zephyr-Core-3.7.0/dts/bindings/misc/ |
| D | nordic,split-channels.yaml | 8 Nordic Split Channels
13 owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
14 child-owned-channels = <7 8 9 10 11>;
16 Which means that channels 0-11 will be assigned to the particular CPU.
18 In addition, `child-owned-channels` property allows to use channels
20 subprocessor(s) assigned, the `child-owned-channels` property
24 owned-channels:
27 List of channels in a split-ownership peripheral that are to be owned
30 nonsecure-channels:
33 List of channels in a split-ownership, split-security peripheral that
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| D | nordic,nrf-dppic-links.yaml | 7 source-channels:
10 Channels that are linked to channels of DPPIC instances on separate
13 sink-channels:
16 Channels that are linked to channels of DPPIC instances on separate
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| D | nxp,s32-emios.yaml | 6 eMIOS provides independent unified channels (UCs), some of channels
8 as a reference timebase (master bus) for other channels.
37 A mask for channels that have internal counter, lsb is channel 0.
48 for channels from 0 to 22, freezed in debug mode:
73 A channel mask for channels that by hardware design can use this master bus
112 for channels use this bus as reference timebase. Could be in range [2 ... 65535]
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| /Zephyr-Core-3.7.0/soc/nordic/nrf53/ |
| D | sync_rtc.c | 71 * @param channels Details about channels
74 static void ppi_ipc_to_rtc(union rtc_sync_channels channels, bool setup) in ppi_ipc_to_rtc() argument
76 nrf_ipc_event_t ipc_evt = nrf_ipc_receive_event_get(channels.ch.ipc_in); in ppi_ipc_to_rtc()
77 uint32_t task_addr = z_nrf_rtc_timer_capture_task_address_get(channels.ch.rtc); in ppi_ipc_to_rtc()
80 nrfx_gppi_task_endpoint_setup(channels.ch.ppi, task_addr); in ppi_ipc_to_rtc()
81 nrf_ipc_publish_set(NRF_IPC, ipc_evt, channels.ch.ppi); in ppi_ipc_to_rtc()
83 nrfx_gppi_task_endpoint_clear(channels.ch.ppi, task_addr); in ppi_ipc_to_rtc()
90 * @param channels Details about channels
93 static void ppi_rtc_to_ipc(union rtc_sync_channels channels, bool setup) in ppi_rtc_to_ipc() argument
95 uint32_t evt_addr = z_nrf_rtc_timer_compare_evt_address_get(channels.ch.rtc); in ppi_rtc_to_ipc()
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| /Zephyr-Core-3.7.0/include/zephyr/devicetree/ |
| D | io-channels.h | 3 * @brief IO channels devicetree macro public API header file.
20 * @defgroup devicetree-io-channels Devicetree IO Channels API
28 * io-channels property at an index
37 * io-channels = <&adc1 10>, <&adc2 20>;
45 * @param node_id node identifier for a node with an io-channels property
46 * @param idx logical index into io-channels property
55 * io-channels property by name
64 * io-channels = <&adc1 10>, <&adc2 20>;
73 * @param node_id node identifier for a node with an io-channels property
74 * @param name lowercase-and-underscores name of an io-channels element
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| /Zephyr-Core-3.7.0/tests/subsys/lorawan/channels_mask/src/ |
| D | main.c | 14 * @brief Test channels mask with size 1
16 * This test will request the channels mask changes, passing valid
32 /* Configure channels mask with expected parameters */ in ZTEST()
34 zassert_equal(err, 0, "Denied right channels mask configuration"); in ZTEST()
36 /* Configure channels mask with unexpected channels mask size */ in ZTEST()
40 /* Configure channels mask with pointer to NULL */ in ZTEST()
46 * @brief Test channels mask with size 6
48 * This test will request the channels mask changes, passing valid
64 /* Configure channels mask with expected parameters */ in ZTEST()
66 zassert_equal(err, 0, "Denied right channels mask configuration"); in ZTEST()
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| /Zephyr-Core-3.7.0/dts/arm/nordic/ |
| D | nrf54h20_cpurad.dtsi | 53 owned-channels = <7 8 9 10 11 12 13 14 15>;
54 child-owned-channels = <8 9 10 11 12>;
55 nonsecure-channels = <8 9 10 11 12>;
62 owned-channels = <0 2 3>;
63 sink-channels = <0 2>;
64 source-channels = <3>;
65 nonsecure-channels = <0 2 3>;
70 owned-channels = <0 2 3>;
71 sink-channels = <3>;
72 source-channels = <0 2>;
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| /Zephyr-Core-3.7.0/drivers/dma/ |
| D | dma_rpi_pico.c | 27 uint32_t channels; member
46 struct dma_rpi_pico_channel *channels; member
115 if (channel >= cfg->channels) { in dma_rpi_pico_config()
116 LOG_ERR("channel must be < %" PRIu32 " (%" PRIu32 ")", cfg->channels, channel); in dma_rpi_pico_config()
175 data->channels[channel].config = dma_channel_get_default_config(channel); in dma_rpi_pico_config()
177 data->channels[channel].source_address = (void *)dma_cfg->head_block->source_address; in dma_rpi_pico_config()
178 data->channels[channel].dest_address = (void *)dma_cfg->head_block->dest_address; in dma_rpi_pico_config()
179 data->channels[channel].block_size = dma_cfg->head_block->block_size; in dma_rpi_pico_config()
180 channel_config_set_read_increment(&data->channels[channel].config, in dma_rpi_pico_config()
183 channel_config_set_write_increment(&data->channels[channel].config, in dma_rpi_pico_config()
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| D | Kconfig.mcux_lpc | 22 int "Number of DMA channels to allocate memory for in driver"
28 is "total number of unique DMA channels ever expected to be used, maximum
30 as many channel data structures as the maximum number of DMA channels
31 in any DMA controller hardware. About 1 KB per 3-4 channels unused can
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| /Zephyr-Core-3.7.0/dts/bindings/mbox/ |
| D | nxp,s32-mru.yaml | 15 to group hardware channel's mailboxes in logical channels.
20 of receive channels on the MRU instance coupled with the core, for instance in
23 channels on which the sender is intended to transmit.
25 For example, core B and C want to send messages to core A in channels 0 and 1,
30 rx-channels = <2>;
47 rx-channels:
51 Number of receive channels enabled on this instance.
52 Setting this value to N, will enable channels 0 to N-1, consecutively.
55 For example, if receiver A wants to Rx on channels 0 and 1, then A must
56 set rx-channels of mruA as follows:
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| D | nxp,mbox-imx-mu.yaml | 12 rx-channels:
16 Number of receive channels enabled on this instance.
17 Setting this value to N, will enable channels 0 to N-1, consecutively.
20 For example, if receiver A wants to Rx on channels 0 to 3, then A must
21 set rx-channels of muA as follows:
24 rx-channels = <4>;
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| D | nxp,mbox-mailbox.yaml | 20 rx-channels:
24 Number of receive channels enabled on this instance.
25 Setting this value to N, will enable channels 0 to N-1, consecutively.
28 For example, if receiver A wants to Rx on channels 0 to 3, then A must
29 set rx-channels of mailbox as follows:
32 rx-channels = <4>;
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| /Zephyr-Core-3.7.0/subsys/task_wdt/ |
| D | task_wdt.c | 40 /* array of all task watchdog channels */
41 static struct task_wdt_channel channels[CONFIG_TASK_WDT_CHANNELS]; variable
68 /* find minimum timeout of all channels */ in schedule_next_timeout()
69 for (int id = 0; id < ARRAY_SIZE(channels); id++) { in schedule_next_timeout()
70 if (channels[id].reload_period != 0 && in schedule_next_timeout()
71 channels[id].timeout_abs_ticks < next_timeout) { in schedule_next_timeout()
73 next_timeout = channels[id].timeout_abs_ticks; in schedule_next_timeout()
113 if (bg_channel || channels[channel_id].reload_period == 0) { in task_wdt_trigger()
118 if (channels[channel_id].callback) { in task_wdt_trigger()
119 channels[channel_id].callback(channel_id, in task_wdt_trigger()
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| /Zephyr-Core-3.7.0/dts/bindings/dma/ |
| D | espressif,esp32-gdma.yaml | 11 The GDMA controller in ESP32-C3 has six independent channels,
12 three transmit channels and three receive channels.
24 The GDMA controller in ESP32-S3 has ten independent channels,
25 five transmit channels and five receive channels. Only six are
26 supported, meaning three transmit and three receive channels.
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| D | nxp,edma.yaml | 13 valid-channels:
18 property and "dma-channels" is the fact that this
21 not going to be using all of the possible channels, thus
23 and "dma-channels" are mutually exclusive, meaning you
32 different configurations (e.g: i.MX93 eDMA3 has 31 channels,
33 i.MX93 eDMA4 has 64 channels and both of them have slightly
38 channels, various flags and offsets. As such, if there's multiple
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| D | st,stm32-dma.yaml | 8 capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
32 offset in the table of channels when mapping to a DMAMUX
34 for 2nd dma instance, offset is the nb of dma channels of the 1st dma,
35 for 3rd dma instance, offset is the nb of dma channels of the 2nd dma
36 plus the nb of dma channels of the 1st dma instance, etc.
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| /Zephyr-Core-3.7.0/tests/drivers/build_all/sensor/ |
| D | adc.dtsi | 14 io-channels = <&test_adc 0>;
20 io-channels = <&test_adc 1>;
30 io-channels = <&test_adc 2>;
48 io-channels = <&test_adc 0>;
58 io-channels = <&test_adc 0>;
67 io-channels = <&test_adc 0>;
76 io-channels = <&adc0 0>;
85 io-channels = <&adc0 0>;
91 io-channels = <&test_adc 0>;
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| /Zephyr-Core-3.7.0/drivers/adc/ |
| D | adc_sam_afec.c | 52 * channels in the sequence: this buffer changes by that amount
53 * so all the channels would get repeated.
57 /* Bit mask of the channels to be sampled. */
58 uint32_t channels; member
113 /* Set single ended channels to unsigned and differential channels in adc_sam_channel_setup()
129 data->channel_id = find_lsb_set(data->channels) - 1; in adc_sam_start_conversion()
133 /* Disable all channels. */ in adc_sam_start_conversion()
151 * all channels as a group.
157 data->channels = ctx->sequence.channels; in adc_context_start_sampling()
193 uint32_t channels = sequence->channels; in start_read() local
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| D | adc_mcp320x.c | 29 uint8_t channels; member
37 uint8_t channels; member
69 if (channel_cfg->channel_id >= config->channels) { in mcp320x_channel_setup()
84 uint8_t channels = 0; in mcp320x_validate_buffer_size() local
88 for (mask = BIT(config->channels - 1); mask != 0; mask >>= 1) { in mcp320x_validate_buffer_size()
89 if (mask & sequence->channels) { in mcp320x_validate_buffer_size()
90 channels++; in mcp320x_validate_buffer_size()
94 needed = channels * sizeof(uint16_t); in mcp320x_validate_buffer_size()
118 if (find_msb_set(sequence->channels) > config->channels) { in mcp320x_start_read()
119 LOG_ERR("unsupported channels in mask: 0x%08x", in mcp320x_start_read()
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| D | adc_gecko.c | 20 /* Number of channels available. */
34 uint32_t channels; member
96 uint32_t channels; in start_read() local
102 if (sequence->channels == 0) { in start_read()
112 /* Verify all requested channels are initialized and store resolution */ in start_read()
113 channels = sequence->channels; in start_read()
115 while (channels) { in start_read()
116 /* Iterate through all channels and check if they are initialized */ in start_read()
117 index = find_lsb_set(channels) - 1; in start_read()
128 channels &= ~BIT(index); in start_read()
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| D | adc_ads7052.c | 25 uint8_t channels; member
33 uint8_t channels; member
60 if (channel_cfg->channel_id >= config->channels) { in adc_ads7052_channel_setup()
70 uint8_t channels = 0; in ads7052_validate_buffer_size() local
73 channels = POPCOUNT(sequence->channels); in ads7052_validate_buffer_size()
75 needed = channels * sizeof(uint16_t); in ads7052_validate_buffer_size()
121 if (find_msb_set(sequence->channels) > config->channels) { in ads7052_start_read()
122 LOG_ERR("unsupported channels in mask: 0x%08x", sequence->channels); in ads7052_start_read()
164 data->channels = ctx->sequence.channels; in adc_context_start_sampling()
240 while (data->channels != 0) { in ads7052_acquisition_thread()
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| /Zephyr-Core-3.7.0/samples/subsys/llext/edk/app/include/ |
| D | app_api.h | 18 enum Channels { enum
27 __syscall int publish(enum Channels channel, void *data,
29 __syscall int receive(enum Channels channel, void *data,
31 __syscall int register_subscriber(enum Channels channel,
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| /Zephyr-Core-3.7.0/tests/bsim/bluetooth/host/l2cap/general/src/ |
| D | main_l2cap_ecred.c | 55 static struct channel channels[L2CAP_CHANNELS]; variable
72 k_work_queue_init(&channels[i].work_queue); in init_workqs()
73 k_work_queue_start(&channels[i].work_queue, stack_area[i], in init_workqs()
106 if (channels[SHORT_MSG_CHAN_IDX].sdus_received != in chan_recv_cb()
107 (channels[LONG_MSG_CHAN_IDX].sdus_received + 1)) { in chan_recv_cb()
207 struct channel *chan = &channels[idx]; in get_free_channel()
214 channels[idx].in_use = true; in get_free_channel()
252 for (int i = 0; i < ARRAY_SIZE(channels); i++) { in disconnect_all_channels()
253 if (channels[i].in_use) { in disconnect_all_channels()
254 LOG_DBG("Disconnecting channel: %d)", channels[i].chan_id); in disconnect_all_channels()
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| /Zephyr-Core-3.7.0/drivers/sensor/ |
| D | default_rtio_sensor.c | 45 * @brief Compute the number of samples needed for the given channels
47 * @param[in] channels Array of channels requested
48 * @param[in] num_channels Number of channels on the @p channels array
49 * @return The number of samples required to read the given channels
51 static inline int compute_num_samples(const struct sensor_chan_spec *const channels, in compute_num_samples() argument
57 num_samples += SENSOR_CHANNEL_3_AXIS(channels[i].chan_type) ? 3 : 1; in compute_num_samples()
94 * @param[in] num_channels The number of valid channels in the header so far
103 if (sensor_chan_spec_eq(header->channels[i], chan_spec)) { in check_header_contains_channel()
119 const struct sensor_chan_spec *const channels = cfg->channels; in sensor_submit_fallback_sync() local
120 const int num_output_samples = compute_num_samples(channels, cfg->count); in sensor_submit_fallback_sync()
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| /Zephyr-Core-3.7.0/doc/hardware/peripherals/sensor/ |
| D | channels.rst | 3 Sensor Channels
6 :dfn:`Channels`, enumerated in :c:enum:`sensor_channel`, are quantities that
9 Sensors may have multiple channels, either to represent different axes of
12 humidity). Sensors may have multiple channels of the same measurement type to
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