| /Zephyr-latest/dts/bindings/usb/ |
| D | usb-audio-hs.yaml | 53 # microphone channel configuration options
54 mic-channel-l:
56 description: Enable (l) channel.
57 mic-channel-r:
59 description: Enable (r) channel.
60 mic-channel-c:
62 description: Enable (c) channel.
63 mic-channel-lfe:
65 description: Enable (lfe) channel.
66 mic-channel-ls:
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| D | usb-audio-hp.yaml | 27 # channel configuration options
28 channel-l:
30 description: Enable (l) channel.
31 channel-r:
33 description: Enable (r) channel.
34 channel-c:
36 description: Enable (c) channel.
37 channel-lfe:
39 description: Enable (lfe) channel.
40 channel-ls:
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| D | usb-audio-mic.yaml | 39 # channel configuration options
40 channel-l:
42 description: Enable (l) channel.
43 channel-r:
45 description: Enable (r) channel.
46 channel-c:
48 description: Enable (c) channel.
49 channel-lfe:
51 description: Enable (lfe) channel.
52 channel-ls:
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| /Zephyr-latest/dts/bindings/usb/uac2/ |
| D | zephyr,uac2-channel-cluster.yaml | 4 description: USB Audio Class 2 Audio Channel Cluster
9 description: Front Left channel present in the cluster
13 description: Front Right channel present in the cluster
17 description: Front Center channel present in the cluster
21 description: Low Frequency Effects channel present in the cluster
25 description: Back Left channel present in the cluster
29 description: Back Right channel present in the cluster
33 description: Front Left of Center channel present in the cluster
37 description: Front Right of Center channel present in the cluster
41 description: Back Center channel present in the cluster
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | Kconfig.rv32m1 | 15 eight channels; each channel has its own level 1 interrupt to
28 bool "INTMUX channel 0"
30 Enable support for INTMUX channel 0.
33 bool "INTMUX channel 1"
35 Enable support for INTMUX channel 1.
38 bool "INTMUX channel 2"
40 Enable support for INTMUX channel 2.
43 bool "INTMUX channel 3"
45 Enable support for INTMUX channel 3.
48 bool "INTMUX channel 4"
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_led_esp32.c | 74 static void pwm_led_esp32_low_speed_update(const struct device *dev, int speed_mode, int channel) in pwm_led_esp32_low_speed_update() argument
79 ledc_hal_ls_channel_update(&data->hal, channel); in pwm_led_esp32_low_speed_update()
83 static void pwm_led_esp32_update_duty(const struct device *dev, int speed_mode, int channel) in pwm_led_esp32_update_duty() argument
87 ledc_hal_set_sig_out_en(&data->hal, channel, true); in pwm_led_esp32_update_duty()
88 ledc_hal_set_duty_start(&data->hal, channel, true); in pwm_led_esp32_update_duty()
90 pwm_led_esp32_low_speed_update(dev, speed_mode, channel); in pwm_led_esp32_update_duty()
94 struct pwm_ledc_esp32_channel_config *channel) in pwm_led_esp32_duty_set() argument
98 ledc_hal_set_hpoint(&data->hal, channel->channel_num, 0); in pwm_led_esp32_duty_set()
99 ledc_hal_set_duty_int_part(&data->hal, channel->channel_num, channel->duty_val); in pwm_led_esp32_duty_set()
100 ledc_hal_set_duty_direction(&data->hal, channel->channel_num, 1); in pwm_led_esp32_duty_set()
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| D | pwm_mc_esp32.c | 103 struct mcpwm_esp32_channel_config *channel) in mcpwm_esp32_duty_set() argument
110 if (channel->inverted) { in mcpwm_esp32_duty_set()
111 duty_type = channel->duty == 0 ? in mcpwm_esp32_duty_set()
112 MCPWM_HAL_GENERATOR_MODE_FORCE_HIGH : channel->duty == 100 ? in mcpwm_esp32_duty_set()
115 duty_type = channel->duty == 0 ? in mcpwm_esp32_duty_set()
116 MCPWM_HAL_GENERATOR_MODE_FORCE_LOW : channel->duty == 100 ? in mcpwm_esp32_duty_set()
120 uint32_t timer_clk_hz = data->mcpwm_clk_hz / config->prescale / channel->prescale; in mcpwm_esp32_duty_set()
122 set_duty = (timer_clk_hz / channel->freq) * channel->duty / 100; in mcpwm_esp32_duty_set()
123 mcpwm_ll_operator_connect_timer(data->hal.dev, channel->operator_id, channel->timer_id); in mcpwm_esp32_duty_set()
124 mcpwm_ll_operator_set_compare_value(data->hal.dev, channel->operator_id, in mcpwm_esp32_duty_set()
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| D | pwm_rv32m1_tpm.c | 40 tpm_chnl_pwm_signal_param_t channel[MAX_CHANNELS]; member
43 static int rv32m1_tpm_set_cycles(const struct device *dev, uint32_t channel, in rv32m1_tpm_set_cycles() argument
52 LOG_ERR("Channel can not be set to inactive level"); in rv32m1_tpm_set_cycles()
56 if (channel >= config->channel_count) { in rv32m1_tpm_set_cycles()
57 LOG_ERR("Invalid channel"); in rv32m1_tpm_set_cycles()
62 data->channel[channel].dutyCyclePercent = duty_cycle; in rv32m1_tpm_set_cycles()
65 data->channel[channel].level = kTPM_HighTrue; in rv32m1_tpm_set_cycles()
67 data->channel[channel].level = kTPM_LowTrue; in rv32m1_tpm_set_cycles()
100 status = TPM_SetupPwm(config->base, data->channel, in rv32m1_tpm_set_cycles()
110 TPM_UpdateChnlEdgeLevelSelect(config->base, channel, in rv32m1_tpm_set_cycles()
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| /Zephyr-latest/drivers/dma/ |
| D | dma_sam_xdmac.c | 31 /* DMA channel configuration */
64 for (int channel = 0; channel < DMA_CHANNELS_NO; channel++) { in sam_xdmac_isr() local
65 if (!(isr_status & (1 << channel))) { in sam_xdmac_isr()
69 channel_cfg = &dev_data->dma_channels[channel]; in sam_xdmac_isr()
71 /* Get channel errors */ in sam_xdmac_isr()
72 err = xdmac->XDMAC_CHID[channel].XDMAC_CIS & XDMAC_INT_ERR; in sam_xdmac_isr()
77 channel, err); in sam_xdmac_isr()
82 int sam_xdmac_channel_configure(const struct device *dev, uint32_t channel, in sam_xdmac_channel_configure() argument
89 if (channel >= DMA_CHANNELS_NO) { in sam_xdmac_channel_configure()
93 /* Check if the channel is enabled */ in sam_xdmac_channel_configure()
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| D | dma_dw_axi.c | 44 /* Channel enable by setting ch_en and ch_en_we */
46 /* Channel enable by setting ch_susp and ch_susp_we */
48 /* Channel enable by setting ch_abort and ch_abort_we */
51 /* channel susp/resume write enable pos */
53 /* channel resume bit pos */
58 /* source address register for a channel */
60 /* destination address register for a channel */
62 /* block transfer size register for a channel */
64 /* channel control register */
66 /* channel configuration register */
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| D | dma_dw_common.c | 37 uint32_t channel; in dw_dma_isr() local
61 channel = find_lsb_set(status_block) - 1; in dw_dma_isr()
62 status_block &= ~(1 << channel); in dw_dma_isr()
63 chan_data = &dev_data->chan[channel]; in dw_dma_isr()
66 LOG_DBG("%s: Dispatching block complete callback fro channel %d", dev->name, in dw_dma_isr()
67 channel); in dw_dma_isr()
75 channel, DMA_STATUS_BLOCK); in dw_dma_isr()
80 channel = find_lsb_set(status_tfr) - 1; in dw_dma_isr()
81 status_tfr &= ~(1 << channel); in dw_dma_isr()
82 chan_data = &dev_data->chan[channel]; in dw_dma_isr()
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| D | dma_xmc4xxx.c | 54 int channel = find_lsb_set(channels_event) - 1; \
57 __ASSERT_NO_MSG(channel >= 0); \
58 dma_channel = &dev_data->channels[channel]; \
61 XMC_DMA_CH_ClearEventStatus(dma, channel, XMC_DMA_CH_##event_test); \
63 dma_channel->cb(dev, dma_channel->user_data, channel, (ret)); \
115 LOG_ERR("Overruns detected on channel %d", i); in dma_xmc4xxx_isr()
123 static int dma_xmc4xxx_config(const struct device *dev, uint32_t channel, struct dma_config *config) in dma_xmc4xxx_config() argument
131 if (channel >= dev_data->ctx.dma_channels) { in dma_xmc4xxx_config()
132 LOG_ERR("Invalid channel number"); in dma_xmc4xxx_config()
142 LOG_ERR("Channel chaining is not supported"); in dma_xmc4xxx_config()
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| D | dma_intel_adsp_hda.c | 31 uint32_t channel, in intel_adsp_hda_dma_host_in_config() argument
39 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_host_in_config()
44 "Unexpected channel direction, HDA host in supports " in intel_adsp_hda_dma_host_in_config()
49 res = intel_adsp_hda_set_buffer(cfg->base, cfg->regblock_size, channel, buf, in intel_adsp_hda_dma_host_in_config()
53 *DGMBS(cfg->base, cfg->regblock_size, channel) = in intel_adsp_hda_dma_host_in_config()
56 intel_adsp_hda_set_sample_container_size(cfg->base, cfg->regblock_size, channel, in intel_adsp_hda_dma_host_in_config()
65 uint32_t channel, in intel_adsp_hda_dma_host_out_config() argument
73 __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); in intel_adsp_hda_dma_host_out_config()
78 "Unexpected channel direction, HDA host out supports " in intel_adsp_hda_dma_host_out_config()
84 res = intel_adsp_hda_set_buffer(cfg->base, cfg->regblock_size, channel, buf, in intel_adsp_hda_dma_host_out_config()
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| D | dma_si32.c | 57 static void dma_si32_isr_handler(const uint8_t channel) in dma_si32_isr_handler() argument
59 const struct SI32_DMADESC_A_Struct *channel_descriptor = &channel_descriptors[channel]; in dma_si32_isr_handler()
60 const dma_callback_t cb = dma_si32_data.channel_data[channel].callback; in dma_si32_isr_handler()
61 void *user_data = dma_si32_data.channel_data[channel].callback_user_data; in dma_si32_isr_handler()
64 LOG_INF("Channel %" PRIu8 " ISR fired", channel); in dma_si32_isr_handler()
66 irq_disable(DMACH0_IRQn + channel); in dma_si32_isr_handler()
69 LOG_ERR("Bus error on channel %" PRIu8, channel); in dma_si32_isr_handler()
77 __ASSERT((SI32_DMACTRL_0->CHENSET.U32 & BIT(channel)) == 0, in dma_si32_isr_handler()
78 "Result of success: Channel disabled"); in dma_si32_isr_handler()
85 cb(DEVICE_DT_INST_GET(0), user_data, channel, result); in dma_si32_isr_handler()
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| D | dma_andes_atcdmac300.c | 70 /* DMA Channel Control Register Definition */
125 /* data for each DMA channel */
151 uint32_t int_status, int_ch_status, channel; in dma_atcdmac300_isr() local
166 channel = find_msb_set(int_ch_status) - 1; in dma_atcdmac300_isr()
167 int_ch_status &= ~(BIT(channel)); in dma_atcdmac300_isr()
169 ch_data = &data->chan[channel]; in dma_atcdmac300_isr()
171 ch_data->blkcallback(dev, ch_data->blkuser_data, channel, 0); in dma_atcdmac300_isr()
173 data->chan[channel].status.busy = false; in dma_atcdmac300_isr()
179 channel = find_msb_set(int_ch_status) - 1; in dma_atcdmac300_isr()
180 int_ch_status &= ~(BIT(channel)); in dma_atcdmac300_isr()
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| D | dma_max32.c | 77 static int max32_dma_config(const struct device *dev, uint32_t channel, struct dma_config *config) in max32_dma_config() argument
84 if (channel >= cfg->channels) { in max32_dma_config()
85 LOG_ERR("Invalid DMA channel - must be < %" PRIu32 " (%" PRIu32 ")", cfg->channels, in max32_dma_config()
86 channel); in max32_dma_config()
90 ch = max32_dma_ch_index(cfg->regs, channel); in max32_dma_config()
92 /* DMA Channel Config */ in max32_dma_config()
106 /* DMA Channel Advanced Config */ in max32_dma_config()
143 /* Enable complete and count-to-zero interrupts for the channel */ in max32_dma_config()
149 data[channel].callback = config->dma_callback; in max32_dma_config()
150 data[channel].cb_data = config->user_data; in max32_dma_config()
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| /Zephyr-latest/tests/boards/intel_adsp/hda/src/ |
| D | dma.c | 47 int res, channel; in ZTEST() local
73 channel = dma_request_channel(dma, NULL); in ZTEST()
74 zassert_true(channel >= 0, "Expected a valid DMA channel"); in ZTEST()
75 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, channel, "dma channel"); in ZTEST()
77 hda_ipc_msg(INTEL_ADSP_IPC_HOST_DEV, IPCCMD_HDA_RESET, channel, IPC_TIMEOUT); in ZTEST()
78 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, channel, "host reset"); in ZTEST()
81 channel | (DMA_BUF_SIZE << 8), IPC_TIMEOUT); in ZTEST()
82 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, channel, "host config"); in ZTEST()
96 res = dma_config(dma, channel, &dma_cfg); in ZTEST()
97 hda_dump_regs(HOST_IN, HDA_REGBLOCK_SIZE, channel, "dsp dma config"); in ZTEST()
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| /Zephyr-latest/samples/bluetooth/iso_peripheral/ |
| D | README.rst | 11 … sample starts advertising, waits for a central to connect to it and set up an isochronous channel.
12 Once the isochronous channel is set up, received isochronous data is printed out.
34 2. Observe that the central device connects and sets up an isochronous channel.
38 ISO Channel 0x20000698 connected
42 Incoming data channel 0x20000698 len 1
44 Incoming data channel 0x20000698 len 2
46 Incoming data channel 0x20000698 len 3
48 Incoming data channel 0x20000698 len 4
50 Incoming data channel 0x20000698 len 5
52 Incoming data channel 0x20000698 len 6
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| /Zephyr-latest/doc/connectivity/bluetooth/shell/host/ |
| D | l2cap.rst | 23 Channel 0x20000210 connected
24 Channel 0x20000210 status 1
29 Outgoing data channel 0x20000210 transmitted
30 Outgoing data channel 0x20000210 transmitted
31 Outgoing data channel 0x20000210 transmitted
38 Channel 0x20000210 status 1
39 Channel 0x20000210 connected
40 Channel 0x20000210 requires buffer
41 Incoming data channel 0x20000210 len 14
43 Channel 0x20000210 requires buffer
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| /Zephyr-latest/drivers/espi/ |
| D | Kconfig | 38 bool "eSPI peripheral channel"
41 eSPI Controller supports peripheral channel.
44 bool "eSPI virtual wire channel"
47 eSPI Controller supports virtual wires channel.
78 early in the flow after the VW channel is configured. Or it could be
79 until flash channel is configured.
82 bool "eSPI Out-of-band channel"
84 eSPI Controller supports OOB channel.
87 bool "ESPI flash channel"
89 eSPI Controller supports flash channel.
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | dma.h | 34 * @brief DMA channel direction
51 * Number of all common channel directions.
82 * @brief DMA channel attributes
85 DMA_CHANNEL_NORMAL, /* normal DMA channel */
183 * @param channel The channel number
191 uint32_t channel, int status);
241 * Channel priority for arbitration, HW specific
248 /** Linked channel, HW specific */
302 /** atomic holding bit flags for each channel to mark as used/unused */
315 typedef int (*dma_api_config)(const struct device *dev, uint32_t channel,
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| /Zephyr-latest/samples/drivers/mbox_data/ |
| D | sample.yaml | 21 - "Client received \\(on channel 2\\) value: 1"
22 - "Client send \\(on channel 3\\) value: 2"
23 - "Client received \\(on channel 2\\) value: 3"
24 - "Client send \\(on channel 3\\) value: 4"
25 - "Client received \\(on channel 2\\) value: 41"
26 - "Client send \\(on channel 3\\) value: 42"
27 - "Client received \\(on channel 2\\) value: 97"
28 - "Client send \\(on channel 3\\) value: 98"
29 - "Client received \\(on channel 2\\) value: 99"
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| /Zephyr-latest/include/zephyr/drivers/timer/ |
| D | nrf_grtc_timer.h | 20 * @param id Compare channel ID.
23 * channel. It can differ from the requested target time
32 /** @brief Allocate GRTC capture/compare channel.
34 * @retval >=0 Non-negative indicates allocated channel ID.
35 * @retval -ENOMEM if channel cannot be allocated.
39 /** @brief Free GRTC capture/compare channel.
41 * @param chan Previously allocated channel ID.
53 * @param chan Channel ID.
64 * @param chan Channel ID.
74 * @param chan Channel ID.
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| /Zephyr-latest/samples/drivers/mbox/ |
| D | sample.yaml | 23 - "Pong \\(on channel 0\\)"
24 - "Ping \\(on channel 1\\)"
41 - "Ping \\(on channel 15\\)"
42 - "Pong \\(on channel 18\\)"
59 - "Ping \\(on channel 16\\)"
60 - "Pong \\(on channel 14\\)"
73 - "Ping \\(on channel 18\\)"
74 - "Pong \\(on channel 12\\)"
84 - "Pong \\(on channel 0\\)"
85 - "Ping \\(on channel 1\\)"
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| /Zephyr-latest/drivers/mbox/ |
| D | mbox_nrfx_ipc.c | 53 uint32_t channel = event_idx; in mbox_dispatcher() local
55 if (!is_rx_channel_valid(dev, channel)) { in mbox_dispatcher()
56 LOG_WRN("RX event on illegal channel"); in mbox_dispatcher()
59 if (!(data->enabled_mask & BIT(channel))) { in mbox_dispatcher()
60 LOG_WRN("RX event on disabled channel"); in mbox_dispatcher()
63 if (data->cb[channel] != NULL) { in mbox_dispatcher()
64 data->cb[channel](dev, channel, data->user_data[channel], NULL); in mbox_dispatcher()
68 static int mbox_nrf_send(const struct device *dev, uint32_t channel, in mbox_nrf_send() argument
75 if (!is_tx_channel_valid(dev, channel)) { in mbox_nrf_send()
79 nrfx_ipc_signal(channel); in mbox_nrf_send()
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