| /Zephyr-Core-3.5.0/drivers/interrupt_controller/ |
| D | Kconfig.rv32m1 | 1 # RV32M1 INTMUX config
4 # SPDX-License-Identifier: Apache-2.0
6 config RV32M1_INTMUX
15 eight channels; each channel has its own level 1 interrupt to
20 config RV32M1_INTMUX_INIT_PRIORITY
27 config RV32M1_INTMUX_CHANNEL_0
28 bool "INTMUX channel 0"
30 Enable support for INTMUX channel 0.
32 config RV32M1_INTMUX_CHANNEL_1
33 bool "INTMUX channel 1"
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| /Zephyr-Core-3.5.0/drivers/espi/ |
| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
22 module-str = espi
25 config ESPI_SLAVE
31 config ESPI_INIT_PRIORITY
37 config ESPI_PERIPHERAL_CHANNEL
38 bool "eSPI peripheral channel"
41 eSPI Controller supports peripheral channel.
43 config ESPI_VWIRE_CHANNEL
44 bool "eSPI virtual wire channel"
47 eSPI Controller supports virtual wires channel.
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| D | Kconfig.xec | 4 # SPDX-License-Identifier: Apache-2.0
6 config ESPI_XEC
13 config ESPI_XEC_V2
22 config ESPI_OOB_CHANNEL
25 config ESPI_FLASH_CHANNEL
28 config ESPI_PERIPHERAL_HOST_IO
31 config ESPI_PERIPHERAL_HOST_IO_PVT
34 config ESPI_PERIPHERAL_DEBUG_PORT_80
37 config ESPI_PERIPHERAL_UART
40 config ESPI_PERIPHERAL_UART_SOC_MAPPING
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| /Zephyr-Core-3.5.0/drivers/pwm/ |
| D | pwm_mcux_tpm.c | 8 * SPDX-License-Identifier: Apache-2.0
25 #define MAX_CHANNELS ARRAY_SIZE(TPM0->CONTROLS)
41 tpm_chnl_pwm_signal_param_t channel[MAX_CHANNELS]; member
44 static int mcux_tpm_set_cycles(const struct device *dev, uint32_t channel, in mcux_tpm_set_cycles() argument
48 const struct mcux_tpm_config *config = dev->config; in mcux_tpm_set_cycles() local
49 struct mcux_tpm_data *data = dev->data; in mcux_tpm_set_cycles()
53 LOG_ERR("Channel can not be set to inactive level"); in mcux_tpm_set_cycles()
54 return -ENOTSUP; in mcux_tpm_set_cycles()
57 if (channel >= config->channel_count) { in mcux_tpm_set_cycles()
58 LOG_ERR("Invalid channel"); in mcux_tpm_set_cycles()
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| D | pwm_rv32m1_tpm.c | 7 * SPDX-License-Identifier: Apache-2.0
24 #define MAX_CHANNELS ARRAY_SIZE(TPM0->CONTROLS)
40 tpm_chnl_pwm_signal_param_t channel[MAX_CHANNELS]; member
43 static int rv32m1_tpm_set_cycles(const struct device *dev, uint32_t channel, in rv32m1_tpm_set_cycles() argument
47 const struct rv32m1_tpm_config *config = dev->config; in rv32m1_tpm_set_cycles() local
48 struct rv32m1_tpm_data *data = dev->data; in rv32m1_tpm_set_cycles()
52 LOG_ERR("Channel can not be set to inactive level"); in rv32m1_tpm_set_cycles()
53 return -ENOTSUP; in rv32m1_tpm_set_cycles()
56 if (channel >= config->channel_count) { in rv32m1_tpm_set_cycles()
57 LOG_ERR("Invalid channel"); in rv32m1_tpm_set_cycles()
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| D | pwm_mcux_sctimer.c | 4 * SPDX-License-Identifier: Apache-2.0
34 sctimer_pwm_signal_param_t channel[CHANNEL_COUNT]; member
38 uint32_t channel, uint32_t period_cycles, in mcux_sctimer_pwm_set_cycles() argument
41 const struct pwm_mcux_sctimer_config *config = dev->config; in mcux_sctimer_pwm_set_cycles() local
42 struct pwm_mcux_sctimer_data *data = dev->data; in mcux_sctimer_pwm_set_cycles()
45 if (channel >= CHANNEL_COUNT) { in mcux_sctimer_pwm_set_cycles()
46 LOG_ERR("Invalid channel"); in mcux_sctimer_pwm_set_cycles()
47 return -EINVAL; in mcux_sctimer_pwm_set_cycles()
51 LOG_ERR("Channel can not be set to inactive level"); in mcux_sctimer_pwm_set_cycles()
52 return -ENOTSUP; in mcux_sctimer_pwm_set_cycles()
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| D | pwm_mcux.c | 4 * SPDX-License-Identifier: Apache-2.0
37 pwm_signal_param_t channel[CHANNEL_COUNT]; member
40 static int mcux_pwm_set_cycles(const struct device *dev, uint32_t channel, in mcux_pwm_set_cycles() argument
44 const struct pwm_mcux_config *config = dev->config; in mcux_pwm_set_cycles() local
45 struct pwm_mcux_data *data = dev->data; in mcux_pwm_set_cycles()
48 if (channel >= CHANNEL_COUNT) { in mcux_pwm_set_cycles()
49 LOG_ERR("Invalid channel"); in mcux_pwm_set_cycles()
50 return -EINVAL; in mcux_pwm_set_cycles()
54 LOG_ERR("Channel can not be set to inactive level"); in mcux_pwm_set_cycles()
55 return -ENOTSUP; in mcux_pwm_set_cycles()
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| D | pwm_mc_esp32.c | 4 * SPDX-License-Identifier: Apache-2.0
94 struct mcpwm_esp32_channel_config *channel) in mcpwm_esp32_duty_set() argument
96 struct mcpwm_esp32_data *data = (struct mcpwm_esp32_data *const)(dev)->data; in mcpwm_esp32_duty_set()
100 if (channel->inverted) { in mcpwm_esp32_duty_set()
101 duty_type = channel->duty == 0 ? in mcpwm_esp32_duty_set()
102 MCPWM_HAL_GENERATOR_MODE_FORCE_HIGH : channel->duty == 100 ? in mcpwm_esp32_duty_set()
105 duty_type = channel->duty == 0 ? in mcpwm_esp32_duty_set()
106 MCPWM_HAL_GENERATOR_MODE_FORCE_LOW : channel->duty == 100 ? in mcpwm_esp32_duty_set()
110 set_duty = mcpwm_ll_timer_get_peak(data->hal.dev, channel->timer_id, false) * in mcpwm_esp32_duty_set()
111 channel->duty / 100; in mcpwm_esp32_duty_set()
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| D | pwm_nxp_s32_emios.c | 4 * SPDX-License-Identifier: Apache-2.0
86 static int pwm_nxp_s32_set_cycles_internal_timebase(uint8_t instance, uint32_t channel, in pwm_nxp_s32_set_cycles_internal_timebase() argument
94 return -EINVAL; in pwm_nxp_s32_set_cycles_internal_timebase()
97 if (Emios_Pwm_Ip_GetPeriod(instance, channel) != period_cycles) { in pwm_nxp_s32_set_cycles_internal_timebase()
98 Emios_Pwm_Ip_SetPeriod(instance, channel, period_cycles); in pwm_nxp_s32_set_cycles_internal_timebase()
102 if (Emios_Pwm_Ip_GetDutyCycle(instance, channel) != pulse_cycles) { in pwm_nxp_s32_set_cycles_internal_timebase()
104 if (Emios_Pwm_Ip_SetDutyCycle(instance, channel, pulse_cycles)) { in pwm_nxp_s32_set_cycles_internal_timebase()
106 return -EIO; in pwm_nxp_s32_set_cycles_internal_timebase()
112 Emios_Pwm_Ip_ForceMatchTrailingEdge(instance, channel, true); in pwm_nxp_s32_set_cycles_internal_timebase()
120 static int pwm_nxp_s32_set_cycles_external_timebase(uint8_t instance, uint32_t channel, in pwm_nxp_s32_set_cycles_external_timebase() argument
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| D | pwm_led_esp32.c | 5 * SPDX-License-Identifier: Apache-2.0
10 /* Include esp-idf headers first to avoid redefining BIT() macro */
52 struct pwm_ledc_esp32_config *config = in get_channel_config() local
53 (struct pwm_ledc_esp32_config *) dev->config; in get_channel_config()
55 for (uint8_t i = 0; i < config->channel_len; i++) { in get_channel_config()
56 if (config->channel_config[i].idx == channel_id) { in get_channel_config()
57 return &config->channel_config[i]; in get_channel_config()
63 static void pwm_led_esp32_low_speed_update(const struct device *dev, int speed_mode, int channel) in pwm_led_esp32_low_speed_update() argument
66 struct pwm_ledc_esp32_data *data = (struct pwm_ledc_esp32_data *const)(dev)->data; in pwm_led_esp32_low_speed_update()
69 ledc_hal_ls_channel_update(&data->hal, channel); in pwm_led_esp32_low_speed_update()
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| D | pwm_mcux_ftm.c | 3 * Copyright (c) 2020-2021 Vestas Wind Systems A/S
5 * SPDX-License-Identifier: Apache-2.0
23 #define MAX_CHANNELS ARRAY_SIZE(FTM0->CONTROLS)
25 /* PWM capture operates on channel pairs */
57 ftm_chnl_pwm_config_param_t channel[MAX_CHANNELS]; member
64 static int mcux_ftm_set_cycles(const struct device *dev, uint32_t channel, in mcux_ftm_set_cycles() argument
68 const struct mcux_ftm_config *config = dev->config; in mcux_ftm_set_cycles() local
69 struct mcux_ftm_data *data = dev->data; in mcux_ftm_set_cycles()
72 uint32_t pair = channel / 2U; in mcux_ftm_set_cycles()
77 LOG_ERR("Channel can not be set to inactive level"); in mcux_ftm_set_cycles()
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| D | pwm_gd32.c | 4 * SPDX-License-Identifier: Apache-2.0
36 /** Flag to indicate if timer has 32-bit counter */
50 /** Obtain channel enable bit for the given channel */
52 /** Obtain polarity bit for the given channel */
54 /** Obtain CHCTL0/1 mask for the given channel (0 or 1) */
60 static int pwm_gd32_set_cycles(const struct device *dev, uint32_t channel, in pwm_gd32_set_cycles() argument
64 const struct pwm_gd32_config *config = dev->config; in pwm_gd32_set_cycles() local
66 if (channel >= config->channels) { in pwm_gd32_set_cycles()
67 return -EINVAL; in pwm_gd32_set_cycles()
70 /* 16-bit timers can count up to UINT16_MAX */ in pwm_gd32_set_cycles()
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| D | pwm_rcar.c | 4 * SPDX-License-Identifier: Apache-2.0
30 #define RCAR_PWM_CR(channel) \ argument
31 ((uint32_t)((channel * RCAR_PWM_REG_SHIFT)) + 0x00) /* PWM Control Register */
32 #define RCAR_PWM_CNT(channel) \ argument
33 ((uint32_t)((channel * RCAR_PWM_REG_SHIFT)) + 0x04) /* PWM Count Register */
41 #define RCAR_PWM_CR_EN BIT(0) /* Channel Enable */
50 #define RCAR_PWM_CNT_PH_MASK 0x000003ff /* PWM High-Level Period */
65 static uint32_t pwm_rcar_read(const struct pwm_rcar_cfg *config, uint32_t offs) in pwm_rcar_read() argument
67 return sys_read32(config->reg_addr + offs); in pwm_rcar_read()
70 static void pwm_rcar_write(const struct pwm_rcar_cfg *config, uint32_t offs, uint32_t value) in pwm_rcar_write() argument
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| D | pwm_b91.c | 4 * SPDX-License-Identifier: Apache-2.0
24 const struct pwm_b91_config *config = dev->config; in pwm_b91_init() local
31 pwm_clk_div = sys_clk.pclk * 1000 * 1000 / config->clock_frequency - 1; in pwm_b91_init()
33 return -EINVAL; in pwm_b91_init()
39 /* Set PWM 32k Channel clock if enabled */ in pwm_b91_init()
40 clk_32k_en |= (config->clk32k_ch_enable & BIT(0)) ? PWM_CLOCK_32K_CHN_PWM0 : 0; in pwm_b91_init()
41 clk_32k_en |= (config->clk32k_ch_enable & BIT(1)) ? PWM_CLOCK_32K_CHN_PWM1 : 0; in pwm_b91_init()
42 clk_32k_en |= (config->clk32k_ch_enable & BIT(2)) ? PWM_CLOCK_32K_CHN_PWM2 : 0; in pwm_b91_init()
43 clk_32k_en |= (config->clk32k_ch_enable & BIT(3)) ? PWM_CLOCK_32K_CHN_PWM3 : 0; in pwm_b91_init()
44 clk_32k_en |= (config->clk32k_ch_enable & BIT(4)) ? PWM_CLOCK_32K_CHN_PWM4 : 0; in pwm_b91_init()
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| D | pwm_sam.c | 4 * SPDX-License-Identifier: Apache-2.0
34 uint32_t channel, uint64_t *cycles) in sam_pwm_get_cycles_per_sec() argument
36 const struct sam_pwm_config *config = dev->config; in sam_pwm_get_cycles_per_sec() local
37 uint8_t prescaler = config->prescaler; in sam_pwm_get_cycles_per_sec()
38 uint8_t divider = config->divider; in sam_pwm_get_cycles_per_sec()
46 static int sam_pwm_set_cycles(const struct device *dev, uint32_t channel, in sam_pwm_set_cycles() argument
50 const struct sam_pwm_config *config = dev->config; in sam_pwm_set_cycles() local
52 Pwm * const pwm = config->regs; in sam_pwm_set_cycles()
55 if (channel >= PWMCHNUM_NUMBER) { in sam_pwm_set_cycles()
56 return -EINVAL; in sam_pwm_set_cycles()
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| D | pwm_sifive.c | 4 * SPDX-License-Identifier: Apache-2.0
21 #define PWM_REG(z_config, _offset) ((mem_addr_t) ((z_config)->base + _offset))
76 const struct pwm_sifive_cfg *config = dev->config; in pwm_sifive_init() local
80 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in pwm_sifive_init()
87 sys_set_bit(PWM_REG(config, REG_PWMCFG), SF_PWMZEROCMP); in pwm_sifive_init()
90 sys_set_bit(PWM_REG(config, REG_PWMCFG), SF_PWMENALWAYS); in pwm_sifive_init()
92 /* Clear IP config bits */ in pwm_sifive_init()
93 sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMSTICKY); in pwm_sifive_init()
94 sys_clear_bit(PWM_REG(config, REG_PWMCFG), SF_PWMDEGLITCH); in pwm_sifive_init()
98 /* Clear the channel comparator */ in pwm_sifive_init()
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| D | pwm_nrf_sw.c | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/gpio/gpio.h>
30 "Only clock-prescaler = <0> is supported when used with RTC");
39 /* One compare channel is needed to set the PWM period, hence +1. */
51 * the counter, so when FORK feature is not available, one more PPI channel
78 static inline NRF_RTC_Type *pwm_config_rtc(const struct pwm_config *config) in pwm_config_rtc() argument
81 return config->rtc; in pwm_config_rtc()
87 static inline NRF_TIMER_Type *pwm_config_timer(const struct pwm_config *config) in pwm_config_timer() argument
90 return config->timer; in pwm_config_timer()
97 uint32_t channel, uint32_t period_cycles, in pwm_period_check() argument
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| D | pwm_xmc4xxx_ccu8.c | 4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/pwm/pwm.h>
38 const struct pwm_xmc4xxx_ccu8_config *config = dev->config; in pwm_xmc4xxx_ccu8_init() local
41 XMC_CCU8_EnableModule(config->ccu8); in pwm_xmc4xxx_ccu8_init()
42 XMC_CCU8_StartPrescaler(config->ccu8); in pwm_xmc4xxx_ccu8_init()
48 .prescaler_initval = config->slice_prescaler[i], in pwm_xmc4xxx_ccu8_init()
53 if (config->slice_prescaler[i] > MAX_SLICE_PRESCALER) { in pwm_xmc4xxx_ccu8_init()
55 config->slice_prescaler[i]); in pwm_xmc4xxx_ccu8_init()
56 return -EINVAL; in pwm_xmc4xxx_ccu8_init()
59 if (config->slice_deadtime_prescaler[i] > MAX_DEADTIME_PRESCALER) { in pwm_xmc4xxx_ccu8_init()
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| /Zephyr-Core-3.5.0/drivers/dma/ |
| D | dma_xmc4xxx.c | 4 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/dma/infineon-xmc4xxx-dma.h>
54 int channel = find_lsb_set(channels_event) - 1; \
57 __ASSERT_NO_MSG(channel >= 0); \
58 dma_channel = &dev_data->channels[channel]; \
60 /* dma_start() and re-enable the event */ \
61 XMC_DMA_CH_ClearEventStatus(dma, channel, XMC_DMA_CH_##event_test); \
62 if (dma_channel->cb) { \
63 dma_channel->cb(dev, dma_channel->user_data, channel, (ret)); \
72 struct dma_xmc4xxx_data *dev_data = dev->data; in dma_xmc4xxx_isr()
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| D | dma_stm32_bdma.c | 4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
278 return -EAGAIN; in stm32_bdma_disable_channel()
288 const struct bdma_stm32_config *config = dev->config; in bdma_stm32_dump_channel_irq() local
289 BDMA_TypeDef *dma = (BDMA_TypeDef *)(config->base); in bdma_stm32_dump_channel_irq()
296 const struct bdma_stm32_config *config = dev->config; in bdma_stm32_clear_channel_irq() local
297 BDMA_TypeDef *dma = (BDMA_TypeDef *)(config->base); in bdma_stm32_clear_channel_irq()
306 const struct bdma_stm32_config *config = dev->config; in bdma_stm32_irq_handler() local
307 BDMA_TypeDef *dma = (BDMA_TypeDef *)(config->base); in bdma_stm32_irq_handler()
308 struct bdma_stm32_channel *channel; in bdma_stm32_irq_handler() local
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| D | dma_mcux_edma.c | 5 * SPDX-License-Identifier: Apache-2.0
113 ((const struct dma_mcux_edma_config *const)dev->config)
114 #define DEV_DATA(dev) ((struct dma_mcux_edma_data *)dev->data)
115 #define DEV_BASE(dev) ((DMA_Type *)DEV_CFG(dev)->base)
118 ((struct call_back *)(&(DEV_DATA(dev)->data_cb[ch])))
121 ((edma_handle_t *)(&(DEV_CHANNEL_DATA(dev, ch)->edma_handle)))
123 #define DEV_DMAMUX_BASE(dev, idx) ((DMAMUX_Type *)DEV_CFG(dev)->dmamux_base[idx])
124 #define DEV_DMAMUX_IDX(dev, ch) (ch / DEV_CFG(dev)->channels_per_mux)
127 (ch % DEV_CFG(dev)->channels_per_mux) ^ (DEV_CFG(dev)->dmamux_reg_offset)
130 * The hardware channel (takes the gap into account) is used when access DMA registers.
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| D | dma_sam0.c | 4 * SPDX-License-Identifier: Apache-2.0
30 /* Handles DMA interrupts and dispatches to the individual channel */
33 struct dma_sam0_data *data = dev->data; in dma_sam0_isr()
35 uint16_t pend = DMA_REGS->INTPEND.reg; in dma_sam0_isr()
36 uint32_t channel; in dma_sam0_isr() local
38 /* Acknowledge all interrupts for the channel in pend */ in dma_sam0_isr()
39 DMA_REGS->INTPEND.reg = pend; in dma_sam0_isr()
41 channel = (pend & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; in dma_sam0_isr()
42 chdata = &data->channels[channel]; in dma_sam0_isr()
45 if (chdata->cb) { in dma_sam0_isr()
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| D | dma_mcux_lpc.c | 2 * Copyright (c) 2020-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
68 ((DMA_Type *)((const struct dma_mcux_lpc_config *const)(dev)->config)->base)
71 ((struct channel_data *)(&(((struct dma_mcux_lpc_dma_data *)dev->data)->channel_data[ch])))
74 ((dma_handle_t *)(&(DEV_CHANNEL_DATA(dev, ch)->dma_handle)))
76 #define EMPTY_OTRIG -1
81 int ret = -EIO; in nxp_lpc_dma_callback()
83 uint32_t channel = handle->channel; in nxp_lpc_dma_callback() local
93 data->busy = DMA_ChannelIsBusy(data->dma_handle.base, channel); in nxp_lpc_dma_callback()
95 data->dma_callback(data->dev, data->user_data, channel, ret); in nxp_lpc_dma_callback()
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| D | Kconfig.dw_common | 4 # SPDX-License-Identifier: Apache-2.0
6 config DMA_DW_FIFO_PARTITION
11 config DMA_DW_LLI_POOL_SIZE
15 The number of LLI structs in a statically allocated pool. Each channel has its own
19 config DMA_DW_HW_LLI
27 config DMA_DW_SUSPEND_DRAIN
31 Rather than immediately stopping a DMA channel the channel is suspended
33 before stopping the channel.
35 config DMA_DW_HOST_MASK
42 config DMA_DW_CHANNEL_COUNT
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| /Zephyr-Core-3.5.0/drivers/counter/ |
| D | counter_mcux_qtmr.c | 2 * Copyright (c) 2022 KT-Elektronik, Klaucke und Partner GmbH
3 * SPDX-License-Identifier: Apache-2.0
11 * Each quad timer module has four channels (0-3) that can operate independently, but the Zephyr
12 * counter-API does not support starting or stopping different channels independently. Hence, each
13 * channel is represented as an independent counter device.
32 qtmr_channel_selection_t channel; member
50 * @brief ISR for a specific timer channel
52 * @param dev timer channel device
56 const struct mcux_qtmr_config *config = dev->config; in mcux_qtmr_timer_handler() local
57 struct mcux_qtmr_data *data = dev->data; in mcux_qtmr_timer_handler()
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