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/Zephyr-Core-3.5.0/dts/bindings/phy/
Dcan-transceiver-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Simple GPIO controlled CAN transceiver
6 compatible: "can-transceiver-gpio"
8 include: can-transceiver.yaml
11 enable-gpios:
12 type: phandle-array
14 GPIO to use to enable/disable the CAN transceiver. This GPIO is driven
15 active when the CAN transceiver is enabled and inactive when the CAN
16 transceiver is disabled.
18 standby-gpios:
[all …]
/Zephyr-Core-3.5.0/drivers/can/transceiver/
DKconfig1 # CAN transceiver configuration options
4 # SPDX-License-Identifier: Apache-2.0
6 menu "CAN transceiver drivers"
9 int "CAN transceiver driver init priority"
12 CAN transceiver device driver initialization priority.
15 bool "GPIO controlled CAN transceiver"
18 depends on GPIO
20 Enable support for GPIO controlled CAN transceivers.
Dcan_transceiver_gpio.c4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/can/transceiver.h>
11 #include <zephyr/drivers/gpio.h>
16 /* Does any devicetree instance have an enable-gpios property? */
20 /* Does any devicetree instance have a standby-gpios property? */
35 const struct can_transceiver_gpio_config *config = dev->config; in can_transceiver_gpio_set_state()
39 if (config->enable_gpio.port != NULL) { in can_transceiver_gpio_set_state()
40 err = gpio_pin_set_dt(&config->enable_gpio, enabled ? 1 : 0); in can_transceiver_gpio_set_state()
42 LOG_ERR("failed to set enable GPIO pin (err %d)", err); in can_transceiver_gpio_set_state()
43 return -EIO; in can_transceiver_gpio_set_state()
[all …]
/Zephyr-Core-3.5.0/dts/bindings/can/
Dcan-controller.yaml1 # Common fields for CAN controllers
6 bus-speed:
11 sample-point:
17 (`sjw`, `prop-seg`, `phase-seg1`, and `phase-seg2`).
25 Initial time quanta of resynchronization jump width (ISO 11898-1).
28 timing parameters. Default of 1 matches the default value previously used for all in-tree CAN
31 Applications can still manually set the SJW using the CAN timing APIs.
32 prop-seg:
36 Initial time quanta of propagation segment (ISO 11898-1). Deprecated in favor of setting
38 phase-seg1:
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Dti,tcan4x5x.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Texas Instruments TCAN4x5x SPI CAN-FD controller.
9 tcan4x5x: can@0 {
12 spi-max-frequency = <18000000>;
13 clock-frequency = <40000000>;
14 device-state-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
15 device-wake-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
16 reset-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
17 int-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
18 bosch,mram-cfg = <0x0 15 15 5 5 0 10 10>;
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/Zephyr-Core-3.5.0/boards/arm/mr_canhubk3/
Dmr_canhubk3.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include "mr_canhubk3-pinctrl.dtsi"
16 model = "NXP MR-CANHUBK3";
24 zephyr,code-partition = &code_partition;
26 zephyr,shell-uart = &lpuart2;
27 zephyr,flash-controller = &mx25l6433f;
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/Zephyr-Core-3.5.0/boards/shields/tcan4550evm/
Dtcan4550evm.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
17 cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
19 tcan4x5x_tcan4550evm: can@0 {
22 /* reduced spi-max-frequency to accommodate flywire connections */
23 spi-max-frequency = <2000000>;
25 clock-frequency = <40000000>;
26 device-state-gpios = <&arduino_header 12 GPIO_ACTIVE_HIGH>; /* D6 */
27 device-wake-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */
28 reset-gpios = <&arduino_header 14 GPIO_ACTIVE_HIGH>; /* D8 */
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/Zephyr-Core-3.5.0/soc/arm/nxp_kinetis/kwx/
Dsoc_kw2xd.c2 * Copyright (c) 2014-2015 Wind River Systems, Inc.
6 * SPDX-License-Identifier: Apache-2.0
33 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
74 * @brief Initialize radio transceiver clock output
76 * The clock output of the transceiver can be used as an input clock
79 * output of the transceiver at 4 MHz. The default frequency of the CLK_OUT
80 * depends on the state of GPIO5 during transceiver reset. The frequency
87 SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK; in set_modem_clock()
88 /* Set PORTB.19 as output - modem RESET pin */ in set_modem_clock()
89 GPIOB->PDDR |= 0x00080000u; in set_modem_clock()
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/Zephyr-Core-3.5.0/boards/arm/atsamc21n_xpro/
Datsamc21n_xpro.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
11 #include "atsamc21n_xpro-pinctrl.dtsi"
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
20 zephyr,shell-uart = &sercom4;
29 pwm-led0 = &pwm_led0;
31 i2c-0 = &sercom1;
35 compatible = "gpio-leds";
43 compatible = "pwm-leds";
50 compatible = "gpio-keys";
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/Zephyr-Core-3.5.0/boards/arm/rcar_h3ulcb/
Drcar_h3ulcb_cr7.dts4 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
10 #include "rcar_h3ulcb_cr7-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 compatible = "renesas,h3ulcb-cr7";
20 zephyr,shell-uart = &scif1;
25 compatible = "gpio-leds";
33 compatible = "gpio-keys";
42 pwm-0 = &pwm0;
50 clock-frequency = <32000>;
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/Zephyr-Core-3.5.0/boards/arm/olimex_stm32_p405/
Dolimex_stm32_p405.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f4/stm32f405rgtx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "Olimex STM32-P405 board";
14 compatible = "olimex,stm32-p405";
18 zephyr,shell-uart = &usart2;
26 compatible = "gpio-leds";
34 compatible = "gpio-keys";
53 clock-frequency = <DT_FREQ_M(8)>;
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/Zephyr-Core-3.5.0/boards/arm/olimexino_stm32/
Dolimexino_stm32.dts2 * Copyright (c) 2017 I-SENSE group of ICCS
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f1/stm32f103r(8-b)tx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "Olimex OLIMEXINO-STM32 board";
18 zephyr,shell-uart = &usart1;
25 compatible = "gpio-leds";
37 compatible = "gpio-keys";
45 transceiver0: can-phy0 {
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/Zephyr-Core-3.5.0/boards/riscv/esp32c3_luatos_core/
Desp32c3_luatos_core.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include "esp32c3_luatos_core-pinctrl.dtsi"
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
17 i2c-0 = &i2c0;
24 compatible = "gpio-keys";
33 compatible = "gpio-leds";
47 clock-frequency = <ESP32_CLK_CPU_160M>;
52 current-speed = <115200>;
53 pinctrl-0 = <&uart0_default>;
54 pinctrl-names = "default";
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/Zephyr-Core-3.5.0/boards/arm/mimxrt1170_evk/
Dmimxrt1170_evk_cm7.dts2 * Copyright 2021-22, NXP
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
13 model = "NXP MIMXRT1170-EVK board";
17 mipi-dsi = &mipi_dsi;
26 zephyr,shell-uart = &lpuart1;
28 zephyr,flash-controller = &is25wp128;
30 zephyr,code-partition = &slot0_partition;
31 zephyr,cpu1-region = &ocram;
36 /* Winbond W9825G6KH-5I */
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/Zephyr-Core-3.5.0/boards/arm/rak4631_nrf52840/doc/
Dindex.rst12 (Bluetooth Low Energy) and the newest LoRa transceiver
15 the same TX power. This makes the RAK4631 an ultra-low
16 power communication solution. RAK4631 can be comfortably
19 .. image:: img/rak4631-front-parts.jpg
21 :alt: RAK4631-NRF52840
31 - nRF52840 ARM Cortex-M4F Processor
32 - 64 MHz CPU clock
33 - 1 Micro-AB USB OTG host/device
34 - Semtech SX1262 low power high range LoRa transceiver
35 - iPEX connectors for the LORA antenna and BLE antenna.
[all …]
/Zephyr-Core-3.5.0/boards/arm/rm1xx_dvk/doc/
Dindex.rst11 Cortex-M0 CPU and on-board Semtech SX1272 LoRa RF chip. This board
12 supports the RM1xx on the RM1xx development board - RM191 for the
20 * :abbr:`GPIO (General Purpose Input Output)`
21 * :abbr:`I2C (Inter-Integrated Circuit)`
28 * :abbr:`UART (Universal asynchronous receiver-transmitter)`
31 .. figure:: img/RM186-DVK.jpg
37 .. figure:: img/RM186-SM.jpg
43 More information about the module can be found on the
63 +-----------+------------+----------------------+
66 | ADC | on-chip | adc |
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/Zephyr-Core-3.5.0/boards/xtensa/olimex_esp32_evb/
Dolimex_esp32_evb.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "olimex_esp32_evb-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "Olimex ESP32-EVB";
15 compatible = "olimex,esp32-evb", "espressif,esp32-wroom-32e", "espressif,esp32";
19 zephyr,shell-uart = &uart0;
30 compatible = "gpio-keys";
32 gpios = <&gpio 34 GPIO_ACTIVE_LOW>;
39 compatible = "regulator-fixed";
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/Zephyr-Core-3.5.0/boards/arm/s32z270dc2_r52/doc/
Dindex.rst3 NXP X-S32Z27X-DC (DC2)
9 The X-S32Z27X-DC (DC2) board is based on the NXP S32Z270 Real-Time Processor,
10 which includes two Real-Time Units (RTU) composed of four ARM Cortex-R52 cores
15 - ``s32z270dc2_rtu0_r52``, for RTU0
16 - ``s32z270dc2_rtu1_r52``, for RTU1.
21 Information about the hardware and design resources can be found at
22 `NXP S32Z2 Real-Time Processors website`_.
29 +-----------+------------+-------------------------------------+
32 | Arm GIC | on-chip | interrupt_controller |
33 +-----------+------------+-------------------------------------+
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/Zephyr-Core-3.5.0/boards/arm/rddrone_fmuk66/
Drddrone_fmuk66.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/pwm/pwm.h>
11 #include "rddrone_fmuk66-pinctrl.dtsi"
21 pwm-led0 = &red_pwm_led;
22 pwm-led1 = &green_pwm_led;
23 pwm-led2 = &blue_pwm_led;
25 red-pwm-led = &red_pwm_led;
26 green-pwm-led = &green_pwm_led;
27 blue-pwm-led = &blue_pwm_led;
[all …]
/Zephyr-Core-3.5.0/drivers/can/
Dcan_mcp2515.h4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/drivers/gpio.h>
12 #include <zephyr/drivers/can.h>
60 /* CAN timing */
69 /* CAN transceiver */
76 * see MCP2515 datasheet section 8.1 Oscillator Start-up Timer
/Zephyr-Core-3.5.0/boards/arm/stm32f3_seco_d23/
Dstm32f3_seco_d23.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f3/stm32f302v(b-c)tx-pinctrl.dtsi>
12 model = "SECO JUNO SBC-D23 board (STM32F302VCT6)";
13 compatible = "seco,stm32f3-d23";
17 zephyr,code-partition = &slot0_partition;
18 zephyr,shell-uart = &usart1;
25 compatible = "gpio-leds";
28 label = "LED-1";
32 label = "LED-2";
[all …]
/Zephyr-Core-3.5.0/boards/arm/b_l072z_lrwan1/doc/
Dindex.rst3 ST B-L072Z-LRWAN1 Discovery kit
9 This Discovery kit features an all-in-one open module CMWX1ZZABZ-091 (by Murata).
10 The module is powered by an STM32L072CZ and an SX1276 transceiver.
14 - CMWX1ZZABZ-091 LoRa* / Sigfox* module (Murata)
16 - Embedded ultra-low-power STM32L072CZ Series MCUs, based on
17 Arm* Cortex* -M0+ core, with 192 Kbytes of Flash
19 - Frequency range: 860 MHz - 930 MHz
20 - USB 2.0 FS
21 - 4-channel,12-bit ADC, 2xDAC
22 - 6-bit timers, LP-UART, I2C and SPI
[all …]
/Zephyr-Core-3.5.0/boards/arm/stm32f3_disco/doc/
Dindex.rst9 The STM32F3DISCOVERY Discovery kit features an ARM Cortex-M4 based STM32F303VC
13 - STM32 microcontroller in LQFP100 package
14 - Extension header for all LQFP100 I/Os for quick connection to prototyping
16 - On-board, ST-LINK/V2 for PCB version A or B or ST-LINK/V2-B for PCB version
18 - Board power supply: through USB bus or from an external 3 V or 5 V supply
20 - External application power supply: 3 V and 5 V
22 - Ten LEDs:
24 - 3.3 V power on (LD1)
25 - USB communication (LD2)
26 - Eight user LEDs: red (LD3/LD10), blue (LD4/LD9), orange (LD5/LD9)
[all …]
/Zephyr-Core-3.5.0/boards/arm/lpcxpresso55s06/
Dlpcxpresso55s06_common.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include "lpcxpresso55s06-pinctrl.dtsi"
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 zephyr,code-partition = &sramx;
17 zephyr,shell-uart = &flexcomm0;
19 zephyr,flash-controller = &iap;
20 zephyr,code-partition = &slot0_partition;
31 usart-0 = &flexcomm0;
35 compatible = "gpio-leds";
51 compatible = "gpio-keys";
[all …]
/Zephyr-Core-3.5.0/boards/arm/lora_e5_dev_board/
Dlora_e5_dev_board.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
8 #include <seeed/lora-e5.dtsi>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 model = "Seeed Studio LoRa-E5 Dev Board";
13 compatible = "seeed,lora-e5-dev-board";
17 zephyr,shell-uart = &usart1;
20 zephyr,code-partition = &flash0;
24 compatible = "gpio-leds";
28 /* the led can be disconnected, using J16 (D5) */
[all …]

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