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| /Zephyr-Core-3.4.0/include/zephyr/retention/ |
| D | bootmode.h | 9 * @brief Public API for boot mode interface
26 * @brief Boot mode interface
27 * @defgroup boot_mode_interface Boot mode interface
33 /** Default (normal) boot, to user application */
36 /** Bootloader boot mode (e.g. serial recovery for MCUboot) */
41 * @brief Checks if the boot mode of the device is set to a specific value.
43 * @param boot_mode Expected boot mode to check.
45 * @retval 1 If successful and boot mode matches.
46 * @retval 0 If boot mode does not match.
52 * @brief Sets boot mode of device.
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| /Zephyr-Core-3.4.0/boards/arm/zybo/doc/ |
| D | index.rst | 52 achieved in a number of ways (e.g. using the Xilinx First Stage Boot Loader (FSBL), the Xilinx
53 Vivado generated ``ps_init.tcl`` JTAG script, Das U-Boot Secondary Program Loader (SPL), ...).
55 The instructions here use the U-Boot SPL. For further details and instructions for using Das U-Boot
58 - `Das U-Boot Website`_
59 - `Using Distro Boot With Xilinx U-Boot`_
61 Building Das U-Boot
64 Clone and build Das U-Boot for the Digilent Zybo:
68 git clone -b v2022.04 https://source.denx.de/u-boot/u-boot.git
69 cd u-boot
82 Ensure the board is configured for JTAG boot, open a serial terminal, turn on/reset the board (press
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| /Zephyr-Core-3.4.0/soc/arm/nxp_imx/rt5xx/ |
| D | Kconfig.soc | 71 bool "The boot header"
74 Enable data structures required by the boot ROM to boot the
80 prompt "Boot device selection"
92 The flash config offset provides the boot ROM with the on-board
93 flash type and parameters. The boot ROM requires a fixed flash config
100 The Image Vector Table (IVT) provides the boot ROM with pointers to
101 the application entry point and device configuration data. The boot
102 ROM requires a fixed IVT offset for each type of boot device.
110 Enable code cache for FlexSPI region at boot. If this Kconfig is
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| /Zephyr-Core-3.4.0/soc/arm/nxp_imx/rt6xx/ |
| D | Kconfig.soc | 77 bool "Boot header"
80 Enable data structures required by the boot ROM to boot the
86 prompt "Boot device selection"
98 The flash config offset provides the boot ROM with the on-board
99 flash type and parameters. The boot ROM requires a fixed flash config
106 The Image Vector Table (IVT) provides the boot ROM with pointers to
107 the application entry point and device configuration data. The boot
108 ROM requires a fixed IVT offset for each type of boot device.
116 Enable code cache for FlexSPI region at boot. If this Kconfig is
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| /Zephyr-Core-3.4.0/boards/x86/acrn/doc/ |
| D | index.rst | 75 the boot filesystem. Under currently tested configurations, Zephyr
153 and Zephyr application will not boot successfully without this change.
198 Assemble EFI Boot Media
201 ACRN will boot on the hardware via the GNU GRUB bootloader, which is
217 Create EFI Boot Filesystem
220 Now attach your boot media (e.g. a USB stick on /dev/sdb, your
221 hardware may differ!) to a Linux system and create an EFI boot
222 partition (type code 0xEF) large enough to store your boot artifacts.
247 "/efi/boot" directory of the boot media. Note that GRUB must be named
252 # mkdir -p /mnt/acrn/efi/boot
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| /Zephyr-Core-3.4.0/boards/x86/ehl_crb/doc/ |
| D | index.rst | 55 Preparing the Boot Device
58 Prepare a USB flash drive to boot the Zephyr application image on
86 Boot the Elkhart Lake CRB board to the EFI shell with USB flash drive connected.
88 #. Insert the prepared boot device (USB flash drive) into the Elkhart Lake CRB board.
109 #. From the EFI shell select Zephyr EFI image to boot.
147 dhcp-boot=zephyr.efi
164 Prepare Elkhart Lake CRB board for network boot
167 #. Enable boot from PXE. Go to EFI shell and make sure that the first boot
172 Shell> bcfg boot dump
179 #. If UEFI PXEv4 is not the first boot option use ``bcfg boot mv`` command to
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| /Zephyr-Core-3.4.0/doc/services/device_mgmt/ |
| D | dfu.rst | 13 * :zephyr_file:`subsys/dfu/boot/`: Interface code to bootloaders
40 The MCUboot API is provided to get version information and boot status of
41 application images. It allows to select application image and boot type
42 for the next boot.
58 `MCUboot boot loader`_. It interfaces with MCUboot and is aware of the image
60 is the boot loader used with Zephyr. The source code itself is hosted in the
88 .. _MCUboot boot loader: https://mcuboot.com/
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| /Zephyr-Core-3.4.0/subsys/retention/ |
| D | Kconfig | 42 bool "Boot mode"
44 Adds a boot mode system that allows for changing execution flow
45 depending upon the value of a boot mode parameter. Can be used for
50 byte must be created and set as the "zephyr,boot-mode" chosen node
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| /Zephyr-Core-3.4.0/tests/kernel/common/src/ |
| D | boot_delay.c | 10 * @brief Test delay during boot
17 * @brief This module verifies the delay specified during boot.
34 /* compare this with the boot delay specified */ in ZTEST()
37 "boot delay not executed: %d < %d", in ZTEST()
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| /Zephyr-Core-3.4.0/soc/arm/nxp_lpc/lpc54xxx/gcc/ |
| D | startup_LPC54114_cm4.S | 68 /* Select boot based on selected master core and core ID */
76 /* Slave boot */
79 ldr r2, [r0] /* r1 = SYSCON co-processor boot address */
81 cmp r2, #0 /* Slave boot address = 0 (not set up)? */
90 /* slave vector table in boot memory */
91 bx r2 /* Jump to slave boot address */
93 /* Slave isn't yet setup for system boot from the master */
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| /Zephyr-Core-3.4.0/doc/services/retention/ |
| D | index.rst | 22 retained data area could be split up into 4 bytes for a boot mode, 16 bytes for
126 Boot mode
129 An addition to the retention subsystem is a boot mode interface, this can be
135 To use the boot mode feature, a data retention entry must exist in the device
136 tree, which is dedicated for use as the boot mode selection (the user area data
138 node of ``zephyr,boot-mode``. See the following example:
164 zephyr,boot-mode = &retention0;
173 The boot mode interface can be enabled with
175 boot mode functions. If using mcuboot with serial recovery, it can be built
195 Boot mode interface
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| /Zephyr-Core-3.4.0/soc/arm/nxp_kinetis/ |
| D | Kconfig | 133 Configures the reset value of the FOPT register, which includes boot,
155 bool "Keep watchdog timer enabled at boot"
157 Leave SOC watchdog timer enabled at boot. The specific timeout
158 and clock configuration of the watchdog at boot is SOC dependent.
159 Note: if the watchdog timer is enabled at boot, the user will
163 # Enable watchdog configuration function if watchdog is left enabled at boot
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| /Zephyr-Core-3.4.0/soc/xtensa/intel_adsp/common/ |
| D | CMakeLists.txt | 16 boot.c
57 DEPENDS ${CMAKE_BINARY_DIR}/zephyr/boot.mod ${CMAKE_BINARY_DIR}/zephyr/main.mod
61 OUTPUT ${CMAKE_BINARY_DIR}/zephyr/boot.mod ${CMAKE_BINARY_DIR}/zephyr/main.mod
80 --only-section .module.boot
81 --set-section-flags .module.boot=noload,readonly
82 --rename-section .module.boot=.module
83 ${KERNEL_REMAPPED} ${CMAKE_BINARY_DIR}/zephyr/boot.mod 2>${NULL_FILE}
89 --remove-section .module.boot
148 ${CMAKE_BINARY_DIR}/zephyr/boot.mod ${CMAKE_BINARY_DIR}/zephyr/main.mod
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| /Zephyr-Core-3.4.0/boards/x86/up_squared/doc/ |
| D | index.rst | 79 Preparing the Boot Device
82 Prepare a USB flash drive to boot the Zephyr application image on
114 Boot the UP Squared board to the EFI shell with USB flash drive connected.
116 #. Insert the prepared boot device (USB flash drive) into the UP Squared board.
137 #. From the EFI shell select Zephyr EFI image to boot.
183 dhcp-boot=zephyr.efi
209 Prepare UP Squared board for network boot
218 #. Make network boot as the first boot option.
222 Boot -> Boot Option #1 : [Network]
250 #. When the boot process completes, you have finished booting the
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| /Zephyr-Core-3.4.0/include/zephyr/arch/x86/ |
| D | efi.h | 10 /* Boot type value (see prep_c.c) */
25 * @param efi_arg The given pointer to EFI prepared boot argument
29 /** @brief Get the ACPI RSDP table pointer from EFI boot argument
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| /Zephyr-Core-3.4.0/drivers/serial/ |
| D | Kconfig.stellaris | 21 This tells the driver to configure the UART port at boot, depending on
29 This tells the driver to configure the UART port at boot, depending on
37 This tells the driver to configure the UART port at boot, depending on
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| /Zephyr-Core-3.4.0/doc/build/dts/ |
| D | dt-vs-kconfig.rst | 12 * Use devicetree to describe **hardware** and its **boot-time configuration**.
13 Examples include peripherals on a board, boot-time clock frequencies,
29 * Additionally, the UART **boot-time configuration** is also described with
32 their boot-time configuration is described in devicetree.
43 * **Boot-time configuration** for the radio, such as TX power in dBm, should
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| /Zephyr-Core-3.4.0/boards/arm/cyclonev_socdk/support/ |
| D | preloader_dl_cmd.txt | 6 restore boards/arm/cyclonev_socdk/support/u-boot-spl
7 symbol-file -readnow boards/arm/cyclonev_socdk/support/u-boot-spl
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| /Zephyr-Core-3.4.0/soc/arm/nxp_kinetis/ke1xf/ |
| D | Kconfig.soc | 82 bool "Keep watchdog timer enabled at boot"
84 Keep the watchdog timer enabled at boot with the internal
87 watchdog timer after boot and install a different timeout,
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| /Zephyr-Core-3.4.0/soc/arm/nxp_imx/rt/ |
| D | Kconfig.soc | 705 bool "Boot header"
708 Enable data structures required by the boot ROM to boot the
714 prompt "Boot device selection"
737 sequence (optional), etc. The boot ROM expects FlexSPI configuration
745 The Image Vector Table (IVT) provides the boot ROM with pointers to
746 the application entry point and device configuration data. The boot
747 ROM requires a fixed IVT offset for each type of boot device.
754 the boot ROM to initialize components such as an SDRAM.
811 Enable Code cache at boot for IMXRT1xxx series
817 Enable Data cache at boot for IMXRT1xxx series
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| /Zephyr-Core-3.4.0/dts/bindings/mfd/ |
| D | nordic,npm6001.yaml | 30 description: Input type for BUCK_MODE0 pin. Defaults IC boot-time value.
40 description: Input type for BUCK_MODE1 pin. Defaults IC boot-time value.
50 description: Input type for BUCK_MODE2 pin. Defaults IC boot-time value.
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| /Zephyr-Core-3.4.0/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/ |
| D | adsp_boot.h | 29 * DSP Boot / Recovery
31 * These registers are added by Intel outside of the Tensilica Core for boot / recovery
32 * control, such as boot path, watch dog timer etc.
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| /Zephyr-Core-3.4.0/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/ |
| D | adsp_boot.h | 29 * DSP Boot / Recovery
31 * These registers are added by Intel outside of the Tensilica Core for boot / recovery
32 * control, such as boot path, watch dog timer etc.
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| /Zephyr-Core-3.4.0/boards/arm64/intel_socfpga_agilex_socdk/ |
| D | intel_socfpga_agilex_socdk_defconfig | 4 # The Zephyr build from this defconfig is expected to boot from
6 # Boot Flow: BL21 -> BL31 -> Zephyr
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| /Zephyr-Core-3.4.0/tests/boot/test_mcuboot/ |
| D | testcase.yaml | 13 boot.mcuboot:
23 boot.mcuboot.assert:
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