Home
last modified time | relevance | path

Searched full:bits (Results 1 – 25 of 1274) sorted by relevance

12345678910>>...51

/Zephyr-Core-3.4.0/drivers/can/
Dcan_stm32fd.c33 * - TEST register SVAL, TXBNS, PVAL, and TXBNP bits are not available.
34 * - CCCR register VMM and UTSU bits are not available.
261 uint32_t bits; in can_stm32fd_read_reg() local
269 err = can_mcan_sys_read_reg(stm32fd_config->base, remap, &bits); in can_stm32fd_read_reg()
278 /* Remap IR bits */ in can_stm32fd_read_reg()
279 *val |= FIELD_PREP(CAN_MCAN_IR_ARA, FIELD_GET(CAN_STM32FD_IR_ARA, bits)); in can_stm32fd_read_reg()
280 *val |= FIELD_PREP(CAN_MCAN_IR_PED, FIELD_GET(CAN_STM32FD_IR_PED, bits)); in can_stm32fd_read_reg()
281 *val |= FIELD_PREP(CAN_MCAN_IR_PEA, FIELD_GET(CAN_STM32FD_IR_PEA, bits)); in can_stm32fd_read_reg()
282 *val |= FIELD_PREP(CAN_MCAN_IR_WDI, FIELD_GET(CAN_STM32FD_IR_WDI, bits)); in can_stm32fd_read_reg()
283 *val |= FIELD_PREP(CAN_MCAN_IR_BO, FIELD_GET(CAN_STM32FD_IR_BO, bits)); in can_stm32fd_read_reg()
[all …]
Dcan_sja1000_priv.h50 /* Mode register (MOD) bits */
57 /* Command Register (CMR) bits */
64 /* Status Register (SR) bits */
74 /* Interrupt Register (IR) bits */
84 /* Interrupt Enable Register (IER) bits */
94 /* Bus Timing Register 0 (BTR0) bits */
101 /* Bus Timing Register 1 (BTR1) bits */
109 /* Error Code Capture register (ECC) bits */
119 /* RX/TX SFF/EFF Frame Information bits */
/Zephyr-Core-3.4.0/include/zephyr/sys/
Dbitarray.h21 /* Number of bits */
27 /* Bundle of bits */
40 * @param total_bits Total number of bits in this bitarray object.
58 * @param total_bits Total number of bits in this bitarray object.
67 * @param total_bits Total number of bits in this bitarray object.
80 * the number of bits in bit array, etc.)
92 * the number of bits in bit array, etc.)
105 * the number of bits in bit array, etc.)
118 * the number of bits in bit array, etc.)
131 * the number of bits in bit array, etc.)
[all …]
Dsys_io.h48 * @brief Output a 16 bits to an I/O port
50 * This function writes a 16 bits to the given port.
52 * @param data the 16 bits to write
53 * @param port the port address where to write the 16 bits
58 * @brief Input 16 bits from an I/O port
60 * This function reads 16 bits from the port.
62 * @param port the port address from where to read the 16 bits
64 * @return the 16 bits read
69 * @brief Output 32 bits to an I/O port
71 * This function writes 32 bits to the given port.
[all …]
/Zephyr-Core-3.4.0/tests/net/buf_simple/src/
Dmain.c53 "Invalid 16 bits byte order"); in ZTEST()
61 "Invalid 16 bits byte order"); in ZTEST()
69 sizeof(le16), "Invalid 16 bits byte order"); in ZTEST()
77 sizeof(be16), "Invalid 16 bits byte order"); in ZTEST()
85 "Invalid 24 bits byte order"); in ZTEST()
93 "Invalid 24 bits byte order"); in ZTEST()
101 sizeof(le24), "Invalid 24 bits byte order"); in ZTEST()
109 sizeof(be24), "Invalid 24 bits byte order"); in ZTEST()
117 "Invalid 32 bits byte order"); in ZTEST()
125 "Invalid 32 bits byte order"); in ZTEST()
[all …]
/Zephyr-Core-3.4.0/tests/bluetooth/uuid/src/
Dtest_bt_uuid_cmp.c19 /* Compare UUID 16 bits */ in ZTEST()
23 /* Compare UUID 128 bits */ in ZTEST()
27 /* Compare UUID 16 bits with UUID 128 bits */ in ZTEST()
31 /* Compare different UUID 16 bits */ in ZTEST()
35 /* Compare different UUID 128 bits */ in ZTEST()
Dtest_bt_uuid_create.c29 /* Compare UUID 16 bits */ in ZTEST()
33 /* Compare UUID 128 bits */ in ZTEST()
37 /* Compare swapped UUID 16 bits */ in ZTEST()
45 /* Compare UUID 16 bits */ in ZTEST()
49 /* Compare UUID 128 bits */ in ZTEST()
53 /* Compare swapped UUID 16 bits */ in ZTEST()
/Zephyr-Core-3.4.0/include/zephyr/net/
Dptp_time.h36 * Seconds are encoded as a 48 bits unsigned integer.
37 * Nanoseconds are encoded as a 32 bits unsigned integer.
40 /** Seconds encoded on 48 bits. */
70 * Seconds are encoded as 48 bits unsigned integer.
71 * Fractional nanoseconds are encoded as 48 bits, their unit
75 /** Seconds encoded on 48 bits. */
91 /** Fractional nanoseconds on 48 bits. */
/Zephyr-Core-3.4.0/dts/bindings/dma/
Dst,stm32u5-dma.yaml21 2. slot: DMA periph request ID, which is written in the REQSEL bits of the CxTR2
37 0x0: Byte (8 bits)
38 0x1: Half-word (16 bits)
39 0x2: Word (32 bits)
42 0x0: Byte (8 bits)
43 0x1: Half-word (16 bits)
44 0x2: Word (32 bits)
Dgd,gd32-dma.yaml25 - 0x0: 8 bits
26 - 0x1: 16 bits
27 - 0x2: 32 bits
31 - 0x0: 8 bits
32 - 0x1: 16 bits
33 - 0x2: 32 bits
Dst,stm32-dmamux.yaml27 0x0: Byte (8 bits)
28 0x1: Half-word (16 bits)
29 0x2: Word (32 bits)
32 0x0: Byte (8 bits)
33 0x1: Half-word (16 bits)
34 0x2: Word (32 bits)
/Zephyr-Core-3.4.0/include/zephyr/drivers/misc/ft8xx/
Dft8xx_common.h29 * @brief Write 1 byte (8 bits) to FT8xx memory
37 * @brief Write 2 bytes (16 bits) to FT8xx memory
45 * @brief Write 4 bytes (32 bits) to FT8xx memory
53 * @brief Read 1 byte (8 bits) from FT8xx memory
62 * @brief Read 2 bytes (16 bits) from FT8xx memory
71 * @brief Read 4 bytes (32 bits) from FT8xx memory
/Zephyr-Core-3.4.0/subsys/bluetooth/controller/
DKconfig.df278 bool "Conversion of IQ samples to 8 bits wide by 4 bits shift"
282 Bluetooth 5.3 Core Specification defines IQ samples to be 8 bits wide: Vol 4, Part E
284 8 bits by ordinary right shift operation by 4 bits. That means there is loss in accuracy
288 bool "Conversion of IQ samples to 8 bits wide by 2 bits shift"
292 Bluetooth 5.3 Core Specification defines IQ samples to be 8 bits wide: Vol 4, Part E
294 8 bits by ordinary right shift operation by 2 bits and a cast to int8_t. That means there
299 bool "Conversion of IQ samples to 8 bits wide by use of 8 LSB"
303 Bluetooth 5.3 Core Specification defines IQ samples to be 8 bits wide: Vol 4, Part E
305 8 bits by use of 8 least significant bits. This conversion may be used only if you are
306 sure actual samples are not greater than 8 bits. This prevents additional accuracy loss
[all …]
/Zephyr-Core-3.4.0/drivers/interrupt_controller/
Dintc_ioapic_priv.h33 /* Version register bits */
40 /* Redirection table entry bits: upper 32 bit */
44 /* Redirection table entry bits: lower 32 bit */
51 /* We care only about the first 14 bits.
52 * The 15th bits is in the first 32bits of RTE but since
/Zephyr-Core-3.4.0/dts/bindings/spi/
Dxlnx,xps-spi-2.00.a.yaml20 xlnx,num-ss-bits:
29 Number of slave select bits implemented
31 xlnx,num-transfer-bits:
39 Number of bits per transfer
/Zephyr-Core-3.4.0/dts/bindings/serial/
Duart-controller.yaml26 stop-bits:
29 Sets the number of stop bits.
35 data-bits:
38 Sets the number of data bits.
/Zephyr-Core-3.4.0/subsys/bluetooth/controller/util/
Dutil.c24 * @brief Population count: Count the number of bits set to 1
61 * bits.
64 * - It shall have at least three ones in the least significant 8 bits.
66 * bits.
131 * significant six bits. in util_aa_le32()
186 * significant 16 bits. in util_aa_le32()
231 uint8_t bits; in util_saa_le32() local
263 * values shall differ in at least two bits. in util_saa_le32()
264 * - Find the number of bits required to support 3 times the maximum in util_saa_le32()
266 * - Clear those number many bits in util_saa_le32()
[all …]
/Zephyr-Core-3.4.0/include/zephyr/dt-bindings/led/
Dseagate_legend_b1414.h12 * 1200 ns -> 7.2 bits
13 * 300 ns -> 1.8 bits
14 * 900 ns -> 5.4 bits
/Zephyr-Core-3.4.0/dts/bindings/crypto/
Dnordic,nrf-ccm.yaml17 length-field-length-8-bits:
21 (8 bits) of the LENGTH field in encrypted/decrypted packets.
22 If not set, only the default length (5 bits) is supported.
/Zephyr-Core-3.4.0/samples/drivers/lcd_hd44780/src/
Dmain.c194 void _pi_lcd_4bits_wr(const struct device *gpio_dev, uint8_t bits) in _pi_lcd_4bits_wr() argument
196 /* High bits */ in _pi_lcd_4bits_wr()
201 if ((bits & BIT(4)) == BIT(4)) { in _pi_lcd_4bits_wr()
204 if ((bits & BIT(5)) == BIT(5)) { in _pi_lcd_4bits_wr()
207 if ((bits & BIT(6)) == BIT(6)) { in _pi_lcd_4bits_wr()
210 if ((bits & BIT(7)) == BIT(7)) { in _pi_lcd_4bits_wr()
217 /* Low bits */ in _pi_lcd_4bits_wr()
222 if ((bits & BIT(0)) == BIT(0)) { in _pi_lcd_4bits_wr()
225 if ((bits & BIT(1)) == BIT(1)) { in _pi_lcd_4bits_wr()
228 if ((bits & BIT(2)) == BIT(2)) { in _pi_lcd_4bits_wr()
[all …]
/Zephyr-Core-3.4.0/drivers/i2c/
Di2c_dw.c67 rx_buffer_depth = ic_comp_param_1.bits.rx_buffer_depth + 1; in i2c_dw_data_ask()
68 tx_buffer_depth = ic_comp_param_1.bits.tx_buffer_depth + 1; in i2c_dw_data_ask()
239 if (intr_stat.bits.rx_full) { in i2c_dw_isr()
252 if (intr_stat.bits.tx_empty) { in i2c_dw_isr()
272 if (intr_stat.bits.stop_det) { in i2c_dw_isr()
285 if (intr_stat.bits.rx_full) { in i2c_dw_isr()
298 if (intr_stat.bits.rd_req) { in i2c_dw_isr()
347 ic_con.bits.master_mode = 1U; in i2c_dw_setup()
348 ic_con.bits.slave_disable = 1U; in i2c_dw_setup()
353 ic_con.bits.restart_en = 1U; in i2c_dw_setup()
[all …]
/Zephyr-Core-3.4.0/include/zephyr/arch/arm64/
Dtpidrro_el0.h9 * @brief tpidrro_el0 bits allocation
13 * aligned, and the address space is 48 bits max. That leaves plenty of
14 * free bits for other purposes.
/Zephyr-Core-3.4.0/samples/drivers/led_ws2812/
Df070rb-bindings.h18 * 1200 ns -> 7.2 bits
19 * 300 ns -> 1.8 bits
20 * 900 ns -> 5.4 bits
/Zephyr-Core-3.4.0/include/zephyr/dt-bindings/interrupt-controller/
Dmchp-xec-ecia.h11 * g = bits[0:4], GIRQ number in [8, 26]
12 * gb = bits[12:8], peripheral source bit position [0, 31] in the GIRQ
13 * na = bits[23:16], aggregated GIRQ NVIC number
14 * nd = bits[31:24], direct NVIC number. For sources without a direct
/Zephyr-Core-3.4.0/tests/net/buf/src/
Dmain.c490 "Invalid 16 bits byte order"); in ZTEST()
498 sizeof(le16), "Invalid 16 bits byte order"); in ZTEST()
500 sizeof(be16), "Invalid 16 bits byte order"); in ZTEST()
509 "Invalid 24 bits byte order"); in ZTEST()
517 sizeof(le24), "Invalid 24 bits byte order"); in ZTEST()
519 sizeof(be24), "Invalid 24 bits byte order"); in ZTEST()
528 "Invalid 32 bits byte order"); in ZTEST()
536 sizeof(le32), "Invalid 32 bits byte order"); in ZTEST()
538 sizeof(be32), "Invalid 32 bits byte order"); in ZTEST()
547 "Invalid 48 bits byte order"); in ZTEST()
[all …]

12345678910>>...51