| /Zephyr-Core-3.4.0/samples/shields/x_nucleo_53l0a1/src/ |
| D | display_7seg.h | 25 #define CHAR_0 (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
26 #define CHAR_1 (BIT(5) | BIT(6))
27 #define CHAR_2 (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(5))
28 #define CHAR_3 (BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
29 #define CHAR_4 (BIT(1) | BIT(2) | BIT(5) | BIT(6))
30 #define CHAR_5 (BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(6))
31 #define CHAR_6 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(6))
32 #define CHAR_7 (BIT(3) | BIT(5) | BIT(6))
33 #define CHAR_8 (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
34 #define CHAR_9 (BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
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| /Zephyr-Core-3.4.0/tests/kernel/common/src/ |
| D | bitfield.c | 14 #define BIT_INDEX(bit) ((3 - ((bit >> 3) & 0x3)) + 4*(bit >> 5)) argument
16 #define BIT_INDEX(bit) (bit >> 3) argument
18 #define BIT_VAL(bit) (1 << (bit & 0x7)) argument
41 unsigned int bit; in ZTEST()
46 for (bit = 0U; bit < 32; ++bit) { in ZTEST()
47 sys_set_bit((mem_addr_t)&b1, bit); in ZTEST()
49 zassert_equal(b1, (1 << bit), in ZTEST()
50 "sys_set_bit failed on bit %d\n", bit); in ZTEST()
52 zassert_true(sys_test_bit((mem_addr_t)&b1, bit), in ZTEST()
53 "sys_test_bit did not detect bit %d\n", bit); in ZTEST()
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| /Zephyr-Core-3.4.0/drivers/sensor/lsm9ds0_mfd/ |
| D | lsm9ds0_mfd.h | 22 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMOR BIT(7)
24 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMOR BIT(6)
26 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMOR BIT(5)
28 #define LSM9DS0_MFD_MASK_STATUS_REG_M_XMOR BIT(4)
30 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMDA BIT(3)
32 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMDA BIT(2)
34 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMDA BIT(1)
36 #define LSM9DS0_MFD_MASK_STATUS_REG_M_XMDA BIT(0)
50 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_XMIEN BIT(7)
52 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_YMIEN BIT(6)
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| /Zephyr-Core-3.4.0/drivers/sensor/lsm6dsl/ |
| D | lsm6dsl.h | 29 #define LSM6DSL_MASK_FUNC_CFG_EN BIT(7)
31 #define LSM6DSL_MASK_FUNC_CFG_EN_B BIT(5)
35 #define LSM6DSL_MASK_SENSOR_SYNC_TIME_FRAME_TPH (BIT(3) | BIT(2) | \
36 BIT(1) | BIT(0))
40 #define LSM6DSL_MASK_SENSOR_SYNC_RES_RATIO (BIT(1) | BIT(0))
44 #define LSM6DSL_MASK_FIFO_CTRL1_FTH (BIT(7) | BIT(6) | \
45 BIT(5) | BIT(4) | \
46 BIT(3) | BIT(2) | \
47 BIT(1) | BIT(0))
51 #define LSM6DSL_MASK_FIFO_CTRL2_TIMER_PEDO_FIFO_EN BIT(7)
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| /Zephyr-Core-3.4.0/drivers/sensor/lsm9ds0_gyro/ |
| D | lsm9ds0_gyro.h | 23 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_DR (BIT(7) | BIT(6))
25 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_BW (BIT(5) | BIT(4))
27 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_PD BIT(3)
29 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_ZEN BIT(2)
31 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_XEN BIT(1)
33 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_YEN BIT(0)
37 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPM (BIT(5) | BIT(4))
39 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPCF (BIT(3) | BIT(2) | BIT(1) | \
40 BIT(0))
43 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I1_INT1 BIT(7)
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| /Zephyr-Core-3.4.0/soc/arm/microchip_mec/mec172x/reg/ |
| D | mec172x_ecia.h | 25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
58 * BLOCK_ACTIVE registers: GIRQ8 is bit[8], ..., GIRQ26 is bit[26].
60 * Each GIRQ is composed of 5 32-bit registers.
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| D | mec172x_i2c_smb.h | 36 * Size 8-bit
40 #define MCHP_I2C_SMB_CTRL_ACK BIT(0)
41 #define MCHP_I2C_SMB_CTRL_STO BIT(1)
42 #define MCHP_I2C_SMB_CTRL_STA BIT(2)
43 #define MCHP_I2C_SMB_CTRL_ENI BIT(3)
45 #define MCHP_I2C_SMB_CTRL_ESO BIT(6)
46 #define MCHP_I2C_SMB_CTRL_PIN BIT(7)
49 #define MCHP_I2C_SMB_STS_NBB BIT(0)
50 #define MCHP_I2C_SMB_STS_LAB BIT(1)
51 #define MCHP_I2C_SMB_STS_AAS BIT(2)
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| /Zephyr-Core-3.4.0/drivers/sensor/apds9960/ |
| D | apds9960.h | 14 #define APDS9960_ENABLE_GEN BIT(6)
15 #define APDS9960_ENABLE_PIEN BIT(5)
16 #define APDS9960_ENABLE_AIEN BIT(4)
17 #define APDS9960_ENABLE_WEN BIT(3)
18 #define APDS9960_ENABLE_PEN BIT(2)
19 #define APDS9960_ENABLE_AEN BIT(1)
20 #define APDS9960_ENABLE_PON BIT(0)
32 #define APDS9960_PERS_PPERS (BIT(4) | BIT(5) | BIT(6) | BIT(7))
33 #define APDS9960_APERS_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
36 #define APDS9960_CONFIG1_WLONG BIT(1)
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| /Zephyr-Core-3.4.0/drivers/ethernet/ |
| D | eth_dwmac_priv.h | 97 #define MAC_CONF_ARPEN BIT(31)
99 #define MAC_CONF_IPC BIT(27)
101 #define MAC_CONF_GPSLCE BIT(23)
102 #define MAC_CONF_S2KP BIT(22)
103 #define MAC_CONF_CST BIT(21)
104 #define MAC_CONF_ACS BIT(20)
105 #define MAC_CONF_WD BIT(19)
106 #define MAC_CONF_BE BIT(18)
107 #define MAC_CONF_JD BIT(17)
108 #define MAC_CONF_JE BIT(16)
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| /Zephyr-Core-3.4.0/drivers/sensor/lps25hb/ |
| D | lps25hb.h | 26 #define LPS25HB_MASK_RES_CONF_AVGT (BIT(3) | BIT(2))
28 #define LPS25HB_MASK_RES_CONF_AVGP (BIT(1) | BIT(0))
32 #define LPS25HB_MASK_CTRL_REG1_PD BIT(7)
34 #define LPS25HB_MASK_CTRL_REG1_ODR (BIT(6) | BIT(5) | BIT(4))
36 #define LPS25HB_MASK_CTRL_REG1_DIFF_EN BIT(3)
38 #define LPS25HB_MASK_CTRL_REG1_BDU BIT(2)
40 #define LPS25HB_MASK_CTRL_REG1_RESET_AZ BIT(1)
42 #define LPS25HB_MASK_CTRL_REG1_SIM BIT(0)
46 #define LPS25HB_MASK_CTRL_REG2_BOOT BIT(7)
48 #define LPS25HB_MASK_CTRL_REG2_FIFO_EN BIT(6)
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| /Zephyr-Core-3.4.0/drivers/sensor/lsm6ds0/ |
| D | lsm6ds0.h | 19 #define LSM6DS0_MASK_ACT_THS_SLEEP_ON_INACT_EN BIT(7)
21 #define LSM6DS0_MASK_ACT_THS_ACT_THS (BIT(6) | BIT(5) | BIT(4) | \
22 BIT(3) | BIT(2) | BIT(1) | \
23 BIT(0))
29 #define LSM6DS0_MASK_INT_GEN_CFG_XL_AOI_XL BIT(7)
31 #define LSM6DSO_MASK_INT_GEN_CFG_XL_6D BIT(6)
33 #define LSM6DS0_MASK_INT_GEN_CFG_XL_ZHIE_XL BIT(5)
35 #define LSM6DS0_MASK_INT_GEN_CFG_XL_ZLIE_XL BIT(4)
37 #define LSM6DS0_MASK_INT_GEN_CFG_XL_YHIE_XL BIT(3)
39 #define LSM6DS0_MASK_INT_GEN_CFG_XL_YLIE_XL BIT(2)
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| /Zephyr-Core-3.4.0/drivers/sensor/lps22hb/ |
| D | lps22hb.h | 22 #define LPS22HB_MASK_INTERRUPT_CFG_AUTORIFP BIT(7)
24 #define LPS22HB_MASK_INTERRUPT_CFG_RESET_ARP BIT(6)
26 #define LPS22HB_MASK_INTERRUPT_CFG_AUTOZERO BIT(5)
28 #define LPS22HB_MASK_INTERRUPT_CFG_RESET_AZ BIT(4)
30 #define LPS22HB_MASK_INTERRUPT_CFG_DIFF_EN BIT(3)
32 #define LPS22HB_MASK_INTERRUPT_CFG_LIR BIT(2)
34 #define LPS22HB_MASK_INTERRUPT_CFG_PL_E BIT(1)
36 #define LPS22HB_MASK_INTERRUPT_CFG_PH_E BIT(0)
43 #define LPS22HB_MASK_CTRL_REG1_ODR (BIT(6) | BIT(5) | BIT(4))
45 #define LPS22HB_MASK_CTRL_REG1_EN_LPFP BIT(3)
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| /Zephyr-Core-3.4.0/soc/riscv/riscv-privileged/neorv32/ |
| D | soc.h | 23 #define NEORV32_SYSINFO_CPU_ZICSR BIT(0)
24 #define NEORV32_SYSINFO_CPU_ZIFENCEI BIT(1)
25 #define NEORV32_SYSINFO_CPU_ZMMUL BIT(2)
26 #define NEORV32_SYSINFO_CPU_ZBB BIT(3)
27 #define NEORV32_SYSINFO_CPU_ZFINX BIT(5)
28 #define NEORV32_SYSINFO_CPU_ZXSCNT BIT(6)
29 #define NEORV32_SYSINFO_CPU_ZXNOCNT BIT(7)
30 #define NEORV32_SYSINFO_CPU_PMP BIT(8)
31 #define NEORV32_SYSINFO_CPU_HPM BIT(9)
32 #define NEORV32_SYSINFO_CPU_DEBUGMODE BIT(10)
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| /Zephyr-Core-3.4.0/include/zephyr/math/ |
| D | ilog2.h | 25 * This calculates the floor of log2 (integer log2) for 32-bit
42 (((n) & BIT(31)) == BIT(31)) ? 31 : \
43 (((n) & BIT(30)) == BIT(30)) ? 30 : \
44 (((n) & BIT(29)) == BIT(29)) ? 29 : \
45 (((n) & BIT(28)) == BIT(28)) ? 28 : \
46 (((n) & BIT(27)) == BIT(27)) ? 27 : \
47 (((n) & BIT(26)) == BIT(26)) ? 26 : \
48 (((n) & BIT(25)) == BIT(25)) ? 25 : \
49 (((n) & BIT(24)) == BIT(24)) ? 24 : \
50 (((n) & BIT(23)) == BIT(23)) ? 23 : \
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| /Zephyr-Core-3.4.0/include/zephyr/arch/arm64/ |
| D | cpu.h | 13 #define DAIFSET_FIQ_BIT BIT(0)
14 #define DAIFSET_IRQ_BIT BIT(1)
15 #define DAIFSET_ABT_BIT BIT(2)
16 #define DAIFSET_DBG_BIT BIT(3)
18 #define DAIFCLR_FIQ_BIT BIT(0)
19 #define DAIFCLR_IRQ_BIT BIT(1)
20 #define DAIFCLR_ABT_BIT BIT(2)
21 #define DAIFCLR_DBG_BIT BIT(3)
23 #define DAIF_FIQ_BIT BIT(6)
24 #define DAIF_IRQ_BIT BIT(7)
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| /Zephyr-Core-3.4.0/drivers/ieee802154/ |
| D | ieee802154_mcr20a_regs.h | 11 * which are used in the macros for the bit field manipulation.
47 #define MCR20A_REG_READ (BIT(7))
48 #define MCR20A_BUF_READ (BIT(7) | BIT(6))
49 #define MCR20A_BUF_BYTE_READ (BIT(7) | BIT(6) | BIT(5))
51 #define MCR20A_BUF_WRITE (BIT(6))
52 #define MCR20A_BUF_BYTE_WRITE (BIT(6) | BIT(5))
119 #define MCR20A_IRQSTS1_RX_FRM_PEND BIT(7)
120 #define MCR20A_IRQSTS1_PLL_UNLOCK_IRQ BIT(6)
121 #define MCR20A_IRQSTS1_FILTERFAIL_IRQ BIT(5)
122 #define MCR20A_IRQSTS1_RXWTRMRKIRQ BIT(4)
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| D | ieee802154_cc2520_regs.h | 63 #define FRMFILT0_FRAME_FILTER_EN BIT(0)
64 #define FRMFILT0_PAN_COORDINATOR BIT(1)
68 #define FRMFILT1_ACCEPT_FT_0_BEACON BIT(3)
69 #define FRMFILT1_ACCEPT_FT_1_DATA BIT(4)
70 #define FRMFILT1_ACCEPT_FT_2_ACK BIT(5)
71 #define FRMFILT1_ACCEPT_FT_3_MAC_CMD BIT(6)
78 #define SRCMATCH_SRC_MATCH_EN BIT(0)
79 #define SRCMATCH_AUTOPEND BIT(1)
80 #define SRCMATCH_PEND_DATAREQ_ONLY BIT(2)
93 #define FRMCTRL0_ENERGY_SCAN BIT(4)
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| /Zephyr-Core-3.4.0/drivers/gpio/ |
| D | gpio_ite_it8xxx2.c | 34 /* gpio port data register (bit mapping to pin) */
38 /* gpio port data mirror register (bit mapping to pin) */
40 /* gpio port output type register (bit mapping to pin) */
129 [IT8XXX2_IRQ_WU20] = {BIT(0), 2, BIT(0)},
130 [IT8XXX2_IRQ_WU21] = {BIT(1), 2, BIT(1)},
131 [IT8XXX2_IRQ_WU22] = {BIT(4), 2, BIT(2)},
132 [IT8XXX2_IRQ_WU23] = {BIT(6), 2, BIT(3)},
133 [IT8XXX2_IRQ_WU24] = {BIT(2), 2, BIT(4)},
134 [IT8XXX2_IRQ_WU40] = {BIT(5), 4, BIT(0)},
135 [IT8XXX2_IRQ_WU45] = {BIT(6), 4, BIT(5)},
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| /Zephyr-Core-3.4.0/drivers/sensor/tmd2620/ |
| D | tmd2620.h | 15 #define TMD2620_ENABLE_WEN BIT(3)
16 #define TMD2620_ENABLE_PEN BIT(2)
17 #define TMD2620_ENABLE_PON BIT(0)
28 * If the WLONG bit is set:
57 #define TMD2620_PERS_PPERS (BIT(4) | BIT(5) | BIT(6) | BIT(7))
60 #define TMD2620_CFG0_WLONG BIT(2)
65 #define TMD2620_PCFG0_PPULSE_LEN_8US BIT(6)
66 #define TMD2620_PCFG0_PPULSE_LEN_16US BIT(7)
67 #define TMD2620_PCFG0_PPULSE_LEN_32US (BIT(6) | BIT(7))
70 #define TMD2620_PCFG0_PPULSE (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5))
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| /Zephyr-Core-3.4.0/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/nrfx_glue/ |
| D | bt_ctlr_used_resources.h | 17 #define HAL_PALNA_GPIOTE_MASK BIT(HAL_PALNA_GPIOTE_CHAN)
25 #define HAL_PDN_CSN_GPIOTE_MASK (BIT(HAL_PDN_GPIOTE_CHAN) | BIT(HAL_CSN_GPIOTE_CHAN))
35 (BIT(HAL_RADIO_ENABLE_TX_ON_TICK_PPI) | \
36 BIT(HAL_RADIO_ENABLE_RX_ON_TICK_PPI) | \
37 BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) | \
38 BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI) | \
39 BIT(HAL_RADIO_END_TIME_CAPTURE_PPI) | \
40 BIT(HAL_EVENT_TIMER_START_PPI) | \
41 BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) | \
42 BIT(HAL_TRIGGER_CRYPT_PPI) | \
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| /Zephyr-Core-3.4.0/dts/riscv/ite/ |
| D | it8xxx2-wuc-map.dtsi | 16 wucs = <&wuc2 BIT(0)>; /* GPD0 */
19 wucs = <&wuc2 BIT(1)>; /* GPD1 */
22 wucs = <&wuc2 BIT(2)>; /* GPC4 */
25 wucs = <&wuc2 BIT(3)>; /* GPC6 */
28 wucs = <&wuc2 BIT(4)>; /* GPD2 */
31 wucs = <&wuc2 BIT(5)>; /* GPE4 */
36 wucs = <&wuc3 BIT(0)>; /* KSI[0] */
39 wucs = <&wuc3 BIT(1)>; /* KSI[1] */
42 wucs = <&wuc3 BIT(2)>; /* KSI[2] */
45 wucs = <&wuc3 BIT(3)>; /* KSI[3] */
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| /Zephyr-Core-3.4.0/drivers/ipm/ |
| D | ipm_nrfx_ipc.h | 52 [0] = BIT(0),
53 [1] = BIT(1),
54 [2] = BIT(2),
55 [3] = BIT(3),
56 [4] = BIT(4),
57 [5] = BIT(5),
58 [6] = BIT(6),
59 [7] = BIT(7),
60 [8] = BIT(8),
61 [9] = BIT(9),
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| /Zephyr-Core-3.4.0/include/zephyr/sys/ |
| D | sys_io.h | 89 * @fn static inline void sys_io_set_bit(io_port_t port, unsigned int bit)
90 * @brief Set the designated bit from port to 1
92 * This functions takes the designated bit starting from port and sets it to 1.
94 * @param port the port address from where to look for the bit
95 * @param bit the designated bit to set (from 0 to n)
99 * @fn static inline void sys_io_clear_bit(io_port_t port, unsigned int bit)
100 * @brief Clear the designated bit from port to 0
102 * This functions takes the designated bit starting from port and sets it to 0.
104 * @param port the port address from where to look for the bit
105 * @param bit the designated bit to clear (from 0 to n)
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| /Zephyr-Core-3.4.0/drivers/can/ |
| D | can_sja1000_priv.h | 51 #define CAN_SJA1000_MOD_RM BIT(0)
52 #define CAN_SJA1000_MOD_LOM BIT(1)
53 #define CAN_SJA1000_MOD_STM BIT(2)
54 #define CAN_SJA1000_MOD_AFM BIT(3)
55 #define CAN_SJA1000_MOD_SM BIT(4)
58 #define CAN_SJA1000_CMR_TR BIT(0)
59 #define CAN_SJA1000_CMR_AT BIT(1)
60 #define CAN_SJA1000_CMR_RRB BIT(2)
61 #define CAN_SJA1000_CMR_CDO BIT(3)
62 #define CAN_SJA1000_CMR_SRR BIT(4)
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| /Zephyr-Core-3.4.0/include/zephyr/arch/common/ |
| D | sys_bitops.h | 24 static ALWAYS_INLINE void sys_set_bit(mem_addr_t addr, unsigned int bit) in sys_set_bit() argument
28 *(volatile uint32_t *)addr = temp | (1 << bit); in sys_set_bit()
31 static ALWAYS_INLINE void sys_clear_bit(mem_addr_t addr, unsigned int bit) in sys_clear_bit() argument
35 *(volatile uint32_t *)addr = temp & ~(1 << bit); in sys_clear_bit()
38 static ALWAYS_INLINE int sys_test_bit(mem_addr_t addr, unsigned int bit) in sys_test_bit() argument
42 return temp & (1 << bit); in sys_test_bit()
60 void sys_bitfield_set_bit(mem_addr_t addr, unsigned int bit) in sys_bitfield_set_bit() argument
62 /* Doing memory offsets in terms of 32-bit values to prevent in sys_bitfield_set_bit()
65 sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F); in sys_bitfield_set_bit()
69 void sys_bitfield_clear_bit(mem_addr_t addr, unsigned int bit) in sys_bitfield_clear_bit() argument
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